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PDF HT49R30 Data sheet ( Hoja de datos )
| Número de pieza | HT49R30 | |
| Descripción | 8-Bit LCD Type MCU | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT49R50
8-Bit Microcontroller
Features
· Operating voltage:
- 2MHz: 3.0V~5.2V
- 2MHz~4MHz: 4.5V~5.5V
· 8 input lines
· 12 bidirectional I/O lines
· Two external interrupt input
· Two 8-bit programmable timer/event
counter with PFD (programmable
frequency divider) function
· LCD driver with 33´3 or 32´4 segments
· 4K´15 program memory EPROM
· 160´8 data memory RAM
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog timer
· Buzzer output
· On-chip crystal and RC oscillator
· Halt function and wake-up feature
reduce power consumption
· 6-level subroutine nesting
· Bit manipulation instruction
· 15-bit table read instruction
· Up to 1ms instruction cycle with 4MHz
system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 80/100-pin QFP package
General Description
The HT49R50 is an 8-bit high performance single
chip microcontroller. Its single cycle instruction
and two-stage pipeline architecture make it suit-
able for high speed applications. The device is
suited for use in multiple LCD low power applica-
tions among which are calculators, clock timers,
games, scales, leisure products, other hand held
LCD products, and battery system in particular.
1 October 22, 1999
1 page  
Pad Assignment
HT49R50
P A 0 /B Z
P A 1 /B Z
PA2
P A 3 /P F D
PA4
PA5
PA6
PA7
P B 0 /IN T 0
P B 1 /IN T 1
P B 2 /T M R 0
P B 3 /T M R 1
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
68
21 22
23 24
67
25 26
27 28
66
(0 ,0 )
29 30
65 64 63
62 61 S E G 1
60 S E G 2
59 S E G 3
58 S E G 4
57 S E G 5
56 S E G 6
55 S E G 7
54 S E G 8
53 S E G 9
52 S E G 10
51 S E G 11
50 S E G 12
49 S E G 13
48 S E G 14
47 S E G 15
46 S E G 16
45 S E G 17
44 S E G 18
43 S E G 19
42 S E G 20
41 S E G 21
40 S E G 22
31 32 33 34 35 36 37 38
39 S E G 23
* The IC substrate should be connected to VSS in the PCB layout artwork.
5 October 22, 1999
5 Page 
HT49R50
· Location 014H
Location 014H is reserved for the Time Base
interrupt service program. If a Time Base in-
terrupt occurs, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 014H.
· Location 018H
Location 018H is reserved for the real time
clock interrupt service program. If a real time
clock interrupt occurs, and the interrupt is
enabled, and the stack is not full, the program
begins execution at location 018H.
· Table location
Any location in the ROM can be used as a
look-up table. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the contents of
the higher-order byte to TBLH (Table
Higher-order byte register) (08H). Only the
destination of the lower-order byte in the ta-
ble is well-defined; the other bits of the table
word are all transferred to the lower portion
of TBLH, and the remaining 1 bit is read as
"0". The TBLH is read only, and the table
pointer (TBLP) is a read/write register (07H),
indicating the table location. Before accessing
the table, the location should be placed in
TBLP. All the table related instructions re-
quire 2 cycles to complete the operation.
These areas may function as a normal ROM
depending upon the user's requirements.
Stack register - STACK
The stack register is a special part of the mem-
ory used to save the contents of the PC. The
stack is organized into 6 levels and is neither
part of the data nor part of the program, and is
neither readable nor writeable. Its activated
level is indexed by a stack pointer (SP) and is
neither readable nor writeable. At a commence-
ment of a subroutine call or an interrupt ac-
knowledgment, the contents of the PC is
pushed onto the stack. At the end of the subrou-
tine or interrupt routine, signaled by a return
instruction (RET or RETI), the contents of the
PC is restored to its previous value from the
stack. After chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag is re-
corded but the acknowledgment is still inhib-
ited. Once the SP is decremented (by RET or
RETI), the interrupt is serviced. This feature
prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the
stack is full, and a "CALL" is subsequently exe-
cuted, a stack overflow occurs and the first en-
try is lost (only the most recent six return
addresses are stored).
Data memory - RAM
The data memory (RAM) is designed with
192´8 bits, and is divided into two functional
groups, namely special function registers and
general purpose data memory, most of which
are readable/writeable, although some are read
only.
Table Location
Instruction(s)
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Note: *11~*0: Table location bits
@7~@0: Table pointer bits
Table location
P11~P8: Current program Counter bits
11 October 22, 1999
11 Page | ||
| Páginas | Total 59 Páginas | |
| PDF Descargar | [ Datasheet HT49R30.PDF ] | |
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