PDF HYB3164160AT-40 Data sheet ( Hoja de datos )

Número de pieza	HYB3164160AT-40
Descripción	4M x 16-Bit Dynamic RAM
Fabricantes	Siemens Semiconductor Group
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No Preview Available ! 4M x 16-Bit Dynamic RAM ( 8k, 4k & 2k Refresh) Advanced Information • 4 194 304 words by 16-bit organization HYB 3164160AT(L) -40/-50/-60 HYB 3165160AT(L) -40/-50/-60 HYB 3166160AT(L) -40/-50/-60 • 0 to 70 °C operating temperature • Fast Page Mode operation • Performance: -40 -50 -60 tRAC RAS access time 40 50 60 ns tCAC CAS access time 10 13 15 ns tAA Access time from address 20 25 30 ns tRC Read/write cycle time 75 90 110 ns tPC Fast page mode cycle time 30 35 40 ns • Single + 3.3 V (± 0.3V) power supply • Low power dissipation: HYB3166160AT(L) HYB3165160AT(L) HYB3164160AT(L) -40 -50 -60 900 558 396 mW 756 468 324 mW 612 378 270 mW 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 µW standby for L-version • Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only) • 2 CAS / 1 WE byte control • 8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT) 4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT) 2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT) • 256 msec refresh period for L-versions • Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 1 page HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM I/O1 I/O2 I/O16 WE .UCAS .LCAS & No. 2 Clock Generator Data in Buffer 16 Data out Buffer 16 OE Column 9 Address A0 Buffer(9) A1 9 Column Decoder A2 A3 Refresh A4 Controller A5 Sense Amplifier I/O Gating 16 A6 A7 Refresh A8 Counter (13) A9 A10 13 512 x16 A11 Row Row Memory Array A12 13 Address Buffers(13) 13 Decoder 8192 8192x512x16 RAS No. 1 Clock Generator Block Diagram for HYB 3164160AT(L) Semiconductor Group 5 5 Page HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM AC Characteristics (cont’d)(note: 6,7,8) TA = 0 to 70 °C,VCC = 3.3 ± 0.3V AC64-2F Parameter Symbol -40 -50 -60 Unit Note min. max. min. max. min. max. CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF – 10 – 13 – 15 ns 12 Output buffer turn-off delay from tOEZ – 10 – 13 – 15 ns 12 OE Data to OE low delay CAS high to data delay OE high to data delay tDZO tCDD tODD 0– 10 – 10 – 0– 13 – 13 – 0– 15 – 15 – ns 13 ns 14 ns 14 Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time CAS delay time from Din tWCH tWP tWCS tR WL tC WL tDS tDH tDZC 5– 5– 0– 10 – 10 – 0– 5– 0– 7– 7– 0– 13 – 13 – 0– 7– 0– 10 – 10 – 0– 15 – 15 – 0– 10 – 0– ns ns ns 15 ns ns ns 16 ns 16 ns 13 Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tR WC tR WD tC WD tA WD tOEH 105 – 55 – 25 – 35 – 5– 126 – 68 – 31 – 43 – 7– 150 – 80 – 35 – 50 – 10 – ns ns 15 ns 15 ns 15 ns Fast Page Mode Cycle Fast page mode cycle time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCPA tRAS tRHPC 30 – 40 25 – 35 25 – 200k 50 – 30 – 40 30 – 200k 60 – 35 – ns 35 ns 200k ns – ns 8 Semiconductor Group 11 11 Page

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