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PDF HYB314265BJL-45 Data sheet ( Hoja de datos )
| Número de pieza | HYB314265BJL-45 | |
| Descripción | 256K x 16-Bit EDO-Dynamic RAM | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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256K x 16-Bit EDO-Dynamic RAM
HYB 514265BJ-400/40/-45/-50
HYB 314265BJ(L)-45/-50
Preliminary Information
• 262 144 words by 16-bit organization
• Power Supply:
• 0 to 70 °C operating temperature
• EDO - Hyper Page Mode
• Performance:
-400 -40 -45 -50
trc 69 69 79 89 ns
trac 40 40 45 50 ns
tcac 10 10 12 13 ns
taa 20 20 22 25 ns
thpc 12,5 15 18 20 ns
thpc 80 66 55 50 MHz
• Low Power dissipation
- Active(max.):
120mA / 120mA / 105mA / 95 mA
- Standby : TTL Inputs (max.) 2.0 mA
- Standby: CMOS Inputs (max.) 1.0 mA
- Standby (L-version)
200 µA
HYB 514265BJ-400 +5 V ±5%
HYB 514265BJ-40 +5 V ±10%
HYB 514265BJ-45 +5 V ±10%
HYB 514265BJ-50 +5 V ±10%
HYB 314265BJ(L)-45 +3.3 V ±0.3 V
HYB 314265BJ(L)-50 +3.3 V ±0.3 V
• Read, write, read-modify-write, CAS -before
RAS refresh, RAS only refresh, hidden refresh
mode
• Low Power Version (L) with Self Refresh
and 250 µA self refresh current
• 2 CAS / 1 WE control
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
512 refresh cycles / 128 ms (L-version)
• Plastic Packages: P-SOJ-40-3 400 mil width
The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process
as well as advanced circuit techniques to provide wide operation margins, both internally and for the
system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a
standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit
densities and is compatible with commonly used automatic testing and insertion equipment.
The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh.
Semiconductor Group
1
6.96
1 page  
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage for HYB 514265................................................ – 0.5 to min. (VCC + 0.5, 7.0) V
Power supply voltage for HYB 514265 ........................................................................... – 1 to + 7 V
Input/output voltage for HYB 314265................................................ – 0.5 to min. (VCC + 0.5, 4.6) V
Power supply voltage for HYB 314265 ..................................................................... – 0.5 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics for HYB514265
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 % (± 5 % for -400 version) , tT = 2 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (IOUT = – 5.0 mA)
Output low voltage (IOUT = 4.2 mA)
Input leakage current, any input
(0 V < VIN < 7 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC)
Average VCC supply current:
-400 version
-40 version
-45 version
-50 version
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during RAS-only
refresh cycles:
-400 version
-40 version
-45 version
-50 version
Symbol Limit Values
min. max.
VIH 2.4 VCC + 0.5
VIL – 0.5 0.8
VOH 2.4 –
VOL –
0.4
II(L) – 10 10
Unit Notes
V1
V1
V1
V1
µA 1
IO(L) – 10 10
µA 1
ICC1
–
ICC2
–
120 mA 2, 3, 4
120
105
95
2 mA –
ICC3
–
120 mA 2, 4
120
105
95
Semiconductor Group
5
5 Page 
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics 5)6)
TA = 0 to 70 ˚C, tT = 2 ns
Parameter
16E
Symbol
Limit Values
Unit Note
-45 -50
min. max. min. max.
Common Parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
CAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
Refresh period (L-version only)
tRC 79 – 89 – ns
tRP 30 – 35 – ns
tRAS 45 10k 50 10k ns
tCAS
7
10k 8
10k ns
tCP 7 – 8 – ns
tASR
0
–
0
–
ns
tRAH
7
–
8
–
ns
tASC
0
–
0
–
ns
tCAH
7
–
8
–
ns
tRCD 11 33 12 37 ns
tRAD
9
23 10 25 ns
tRSH 12
13 –
ns
tCSH 36
40 –
ns
tCRP
5
–
5
–
ns
tT 1 50 1 50 ns 7
tREF –
16 –
16 ms
tREF –
128 –
128 ms
Read Cycle
Access time from RAS
tRAC
–
45 –
50 ns 8, 9
Access time from CAS
tCAC
–
12 –
13 ns 8, 9
Access time from column address
tAA – 22 – 25 ns 8,10
OE access time
tOEA
–
12 –
13 ns
Column address to RAS lead time
tRAL 23 –
25 –
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns 11
Read command hold time referenced to RAS tRRH 0 – 0 – ns 11
CAS to output in low-Z
tCLZ 0 – 0 – ns 8
Semiconductor Group
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet HYB314265BJL-45.PDF ] | |
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