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ADG715 の電気的特性と機能

ADG715のメーカーはAnalog Devicesです、この部品の機能は「CMOS/ Low Voltage Serially-Controlled/ Octal SPST Switches」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADG715
部品説明 CMOS/ Low Voltage Serially-Controlled/ Octal SPST Switches
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADG715 Datasheet, ADG715 PDF,ピン配置, 機能
a CMOS, Low Voltage
Serially-Controlled, Octal SPST Switches
ADG714/ADG715
FEATURES
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I2C™-Compatible Interface
2.7 V to 5.5 V Single Supply
؎3 V Dual Supply
2.5 On Resistance
0.6 On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
FUNCTIONAL BLOCK DIAGRAMS
ADG714
S1
S2
S3
S4
S5
S6
S7
S8
INPUT SHIFT
REGISTER
D1 S1
D2 S2
D3 S3
D4 S4
D5 S5
D6 S6
D7 S7
D8 S8
DOUT
ADG715
INTERFACE
LOGIC
SCLK DIN SYNC RESET
SDA SCL A0 A1
D1
D2
D3
D4
D5
D6
D7
D8
RESET
GENERAL DESCRIPTION
The ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a two- or 3-wire
serial interface. On resistance is closely matched between switches
and very flat over the full signal range. Each switch conducts
equally well in both directions and the input signal range extends
to the supplies. Data is written to these devices in the form of
8 bits, each bit corresponding to one channel.
The ADG714 utilizes a 3-wire serial interface that is compatible
with SPI , QSPI and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.
The ADG715 utilizes a 2-wire serial interface that is compatible
with the I2C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by the
user. A maximum of four of these devices may be connected to
the bus.
On power-up of these devices, all switches are in the OFF con-
dition, and the internal registers contain all zeros.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual ± 3 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS
1. 2-3-Wire Serial Interface.
2. Single/Dual Supply Operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and ± 3 V
supply rails.
3. Low On Resistance, typically 2.5 .
4. Low Leakage.
5. Power-On Reset.
6. Small 24-lead TSSOP package.
I2C is a trademark of Philips Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 Page





ADG715 pdf, ピン配列
SPECIFICATIONS1
(VDD = 3 V ؎ 10%, VSS = 0 V, GND = 0 V unless otherwise noted)
ADG714/ADG715
Parameter
B Version
–40؇C
+25؇C to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between Channels (RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT2
Output Low Voltage
COUT Digital Output Capacitance
DIGITAL INPUTS (SCL, SDA)2
Input High Voltage, VINH
Input Low Voltage, VINL
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
DYNAMIC CHARACTERISTICS2
tON ADG714
tON ADG715
tOFF ADG714
tOFF ADG715
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
6
11
± 0.01
± 0.1
± 0.01
± 0.1
± 0.01
± 0.1
0.005
3
4
0.005
0.05 VDD
6
35
130
11
115
8
±2
–60
–80
–70
–90
155
11
11
22
10
0 V to VDD V
typ
12 max
0.4 typ
1.2 max
3.5 typ
nA typ
± 0.3 nA max
nA typ
± 0.3 nA max
nA typ
± 0.3 nA max
2.0 V min
0.4 V max
µA typ
± 0.1 µA max
pF typ
0.4 max
pF typ
0.7 VDD
VDD + 0.3
–0.3
0.3 VDD
±1
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
0.4 V max
0.6 V max
ns typ
65 ns max
ns typ
200 ns max
ns typ
20 ns max
ns typ
180 ns max
ns typ
1 ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
µA typ
20 µA max
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD , IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V
VS = 1 V/3 V, VD = 3 V/1 V
VS = VD = 1 V, or 3 V
VIN = VINL or VINH
ISINK = 6 mA
VIN = 0 V to VDD
ISINK = 3 mA
ISINK = 6 mA
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 1.5 V, RS = 0 , CL = 1 nF
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–


3Pages


ADG715 電子部品, 半導体
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1 (VDD = 2.7 V to 5.5 V. All specifications –40؇C to +85؇C unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCL 400
t1 2.5
t2 0.6
t3 1.3
t4 0.6
t5 100
t62 0.9
0
t7 0.6
t8 0.6
t9 1.3
t10 300
20 + 0.1Cb3
t11 250
t11 300
20 + 0.1Cb3
Cb 400
tSP4 50
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns max
ns min
pF max
ns max
SCL Clock Frequency
SCL Cycle Time
tHIGH, SCL High Time
tLOW, SCL Low Time
tHD, STA, Start/Repeated Start Condition Hold Time
tSU, DAT, Data Setup Time
tHD, DAT, Data Hold Time
tSU, STA, Setup Time for Repeated Start
tSU, STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and
a Start Condition
tR, Rise Time of both SCL and SDA when Receiving
tF, Fall Time of SDA When Receiving
tF, Fall Time of SDA when Transmitting
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
NOTES
1See Figure 2.
2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
4Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
SDA
t9 t3
t10
t11
t4
SCL
t4
START
CONDITION
t2
t6
t5 t7 t1
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
STOP
CONDITION
–6– REV. 0

6 Page



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共有リンク

Link :


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