DataSheet.jp

ADC08060CIMT の電気的特性と機能

ADC08060CIMTのメーカーはNational Semiconductorです、この部品の機能は「8-Bit/ 20 MSPS to 60 MSPS/ 1.3 mW/MSPS A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADC08060CIMT
部品説明 8-Bit/ 20 MSPS to 60 MSPS/ 1.3 mW/MSPS A/D Converter
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




このページの下部にプレビューとADC08060CIMTダウンロード(pdfファイル)リンクがあります。

Total 19 pages

No Preview Available !

ADC08060CIMT Datasheet, ADC08060CIMT PDF,ピン配置, 機能
January 2003
ADC08060
8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
General Description
The ADC08060 is a low-power, 8-bit, monolithic analog-to-
digital converter with an on-chip track-and-hold circuit. Opti-
mized for low cost, low power, small size and ease of use,
this product operates at conversion rates of 20 MSPS to 70
MSPS with outstanding dynamic performance over its full
operating range while consuming just 1.3 mW per MHz of
clock frequency. That’s just 78 mW of power at 60 MSPS.
Raising the PD pin puts the ADC08060 into a Power Down
mode where it consumes just 1 mW.
The unique architecture achieves 7.5 Effective Bits with
25 MHz input frequency. The excellent DC and AC charac-
teristics of this device, together with its low power consump-
tion and single +3V supply operation, make it ideally suited
for many imaging and communications applications, includ-
ing use in portable equipment. Furthermore, the ADC08060
is resistant to latch-up and the outputs are short-circuit proof.
The top and bottom of the ADC08060’s reference ladder are
available for connections, enabling a wide range of input
possibilities. The digital outputs are TTL/CMOS compatible
with a separate output power supply pin to support interfac-
ing with 3V or 2.5V logic. The digital inputs (CLK and PD) are
TTL/CMOS compatible.
The ADC08060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40˚C to +85˚C.
Features
n Single-ended input
n Internal sample-and-hold function
n Low voltage (single +3V) operation
n Small package
n Power-down feature
Key Specifications
n Resolution
8 bits
n Maximum sampling frequency
60 MSPS (min)
n DNL
0.4 LSB (typ)
n ENOB
7.5 bits (typ) at fIN = 25 MHz
n THD
−60 dB (typ)
n No missing codes
Guaranteed
n Power Consumption
n Operating
1.3 mW/MSPS (typ)
n Power down
1 mW (typ)
Applications
n Digital imaging systems
n Communication systems
n Portable instrumentation
n Viterbi decoders
n Set-top boxes
Pin Configuration
© 2003 National Semiconductor Corporation DS200062
20006201
www.national.com

1 Page





ADC08060CIMT pdf, ピン配列
Pin Descriptions and Equivalent Circuits (Continued)
Pin No.
Symbol
Equivalent Circuit
Description
23 PD
Power Down input. When this pin is high, the converter is
in the Power Down mode and the data output pins hold
the last conversion result.
24 CLK
CMOS/TTL compatible digital clock Input. VIN is sampled
on the falling edge of CLK input.
13 thru 16
and
19 thru 22
D0–D7
7
1, 4, 12
VIN GND
VA
18
17
2, 5, 8, 11
DR VD
DR GND
AGND
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input.
Reference ground for the single-ended analog input, VIN.
Positive analog supply pin. Connect to a clean, quiet
voltage source of +3V. VA should be bypassed with a 0.1
µF ceramic chip capacitor for each pin, plus one
10 µF capacitor. See Section 3.0 for more information.
Power supply for the output drivers. If connected to VA,
decouple well from VA.
The ground return for the output driver supply.
The ground return for the analog supply.
3 www.national.com


3Pages


ADC08060CIMT 電子部品, 半導体
Converter Electrical Characteristics (Continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50%
duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
DC Input
76 96 mW (max)
PC Power Consumption
fIN = 10 MHz, VIN = FS − 3 dB,
PD = Low
88
mW
CLK Low, PD = Hi
0.6 mW
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
FSE change with 2.7V to 3.3V change
in VA
SNR change with 200 mV at 200 kHz
on supply
54
45
dB
dB
AC ELECTRICAL CHARACTERISTICS
fC1 Maximum Conversion Rate
fC2 Minimum Conversion Rate
tCL Minimum Clock Low Time
tCH Minimum Clock High Time
tOH Output Hold Time
tOD Output Delay
Pipeline Delay (Latency)
CLK Rise to Data Invalid
CLK Rise to Data Valid
70 60 MHz (min)
20 MHz
6.7 ns (min)
6.7 ns (min)
4.4 ns
8.2 12 ns (max)
2.5 Clock Cycles
tAD Sampling (Aperture) Delay
tAJ Aperture Jitter
CLK Fall to Acquisition of Data
1.5
2
ns
ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. In the 24-pin
TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 435 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
this device under normal operation will typically be about 180 mW (88 mW quiescent power +12 mW reference ladder power). The values for maximum power
dissipation listed above will be reached only when the ADC08060 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input
voltage must be 2.6VDC to ensure accurate conversions.
20006207
Note 8: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
www.national.com
6

6 Page



ページ 合計 : 19 ページ
 
PDF
ダウンロード
[ ADC08060CIMT データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ADC08060CIMT

8-Bit/ 20 MSPS to 60 MSPS/ 1.3 mW/MSPS A/D Converter

National Semiconductor
National Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap