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AD9833 の電気的特性と機能

AD9833のメーカーはAnalog Devicesです、この部品の機能は「Programmable Waveform Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9833
部品説明 Programmable Waveform Generator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9833 Datasheet, AD9833 PDF,ピン配置, 機能
Data Sheet
FEATURES
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion,
and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
AD9833
GENERAL DESCRIPTION
The AD9833 is a low power, programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry (TDR) applications.
The output frequency and phase are software programmable,
allowing easy tuning. No external components are needed. The
frequency registers are 28 bits wide: with a 25 MHz clock rate,
resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate,
the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This function
allows sections of the device that are not being used to be powered
down, thus minimizing the current consumption of the part. For
example, the DAC can be powered down when a clock output is
being generated.
The AD9833 is available in a 10-lead MSOP package.
AGND DGND
FUNCTIONAL BLOCK DIAGRAM
VDD
CAP/2.5V
MCLK
AVDD/
DVDD
REGULATOR
2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
FREQ0 REG
FREQ1 REG
MUX
PHASE
ACCUMUL ATOR
(28-BIT)
PHASE0 REG
PHASE1 REG
MUX
CONTROL REGISTER
SERIAL INTERFACE
AND
CONTROL LOGIC
12
SIN
MUX
10-BIT DAC
ROM
MSB
DIVIDE
BY 2
MUX
AD9833
R
200Ω
COMP
VOUT
FSYNC SCLK SDATA
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





AD9833 pdf, ピン配列
• AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
• AN-953: Direct Digital Synthesis (DDS) with a
Programmable Modulus
Data Sheet
• AD9833-DSCC: Military Data Sheet
• AD9833-EP: Enhanced Product Data Sheet
• AD9833: Low Power 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator Data Sheet
Product Highlight
• Introducing Digital Up/Down Converters: VersaCOMM™
Reconfigurable Digital Converters
Technical Books
• A Technical Tutorial on Digital Signal Synthesis, 1999
User Guides
• UG-272: Evaluating the AD9833 Low Power 12.65 mW,
2.3 V to 5.5 V, Programmable Waveform Generator
Software and Systems Requirements
• AD9833 - Microcontroller No-OS Driver
• AD9834 IIO Direct Digital Synthesis Linux Driver
• AD9833 Evaluation Board Software
• AD9833 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
• BeMicro FPGA Project for AD9833 with Nios driver
Tools and Simulations
• ADIsimDDS (Direct Digital Synthesis)
• AD9833 IBIS Model
Reference Materials
Technical Articles
• 400-MSample DDSs Run On Only +1.8 VDC
• ADI Buys Korean Mobile TV Chip Maker
• Basics of Designing a Digital Radio Receiver (Radio 101)
• Clock Requirements For Data Converters
• DDS Applications
• DDS Circuit Generates Precise PWM Waveforms
• DDS Design
• DDS Device Produces Sawtooth Waveform
• DDS Device Provides Amplitude Modulation
• DDS IC Initiates Synchronized Signals
• DDS IC Plus Frequency-To-Voltage Converter Make Low-
Cost DAC
• DDS Simplifies Polar Modulation
• Digital Potentiometers Vary Amplitude In DDS Devices
• Digital Up/Down Converters: VersaCOMM™ White Paper
• Digital Waveform Generator Provides Flexible Frequency
Tuning for Sensor Measurement
• Improved DDS Devices Enable Advanced Comm Systems
• Integrated DDS Chip Takes Steps To 2.7 GHz
• Simple Circuit Controls Stepper Motors
• Speedy A/Ds Demand Stable Clocks
• Synchronized Synthesizers Aid Multichannel Systems
• The Year of the Waveform Generator
• Two DDS ICs Implement Amplitude-shift Keying
• Video Portables and Cameras Get HDMI Outputs
Design Resources
• AD9833 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9833 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.


3Pages


AD9833 電子部品, 半導体
AD9833
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8 min
t8 max
t9
t10
t11
Limit at TMIN to TMAX
40
16
16
25
10
10
5
10
t4 − 5
5
3
5
1 Guaranteed by design, not production tested.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
SCLK high to FSYNC falling edge setup time
Data Sheet
Timing Diagrams
t1
MCLK
t2
t3
Figure 3. Master Clock
SCLK
FSYNC
t11
SDATA
t5
t7 t6
t4
t8
D15 D14
t10
t9
D2 D1
Figure 4. Serial Timing
D0
D15 D14
Rev. E | Page 4 of 24

6 Page



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共有リンク

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