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PDF AM27F010-70FE Data sheet ( Hoja de datos )
| Número de pieza | AM27F010-70FE | |
| Descripción | 1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt/ Bulk Erase Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
Am28F010
1 Megabit (128 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance
— 70 ns maximum access time
s CMOS Low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
s Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s 10,000 write/erase cycles minimum
s Write and erase voltage 12.0 V ±5%
s Latch-up protected to 100 mA
from –1 V to VCC +1 V
s Flasherase™ Electrical Bulk Chip-Erase
— One second typical chip-erase
s Flashrite™ Programming
— 10 µs typical byte-program
— Two seconds typical chip program
s Command register architecture for
microprocessor/microcontroller compatible
write interface
s On-chip address and data latches
s Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F010 is a 1 Megabit Flash memory orga-
nized as 128 Kbytes of 8 bits each. AMD’s Flash mem-
ories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
Am28F010 is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed
and erased in-system or in standard EPROM pro-
grammers. The Am28F010 is erased when shipped
from the factory.
The standard Am28F010 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F010 has separate chip enable (CE#) and
output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F010 uses a command register to manage this
functionality, while maintaining a JEDEC Flash Stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintain-
ing maximum EPROM compatibility.
AMD’s Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-
gramming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F010 uses a
12.0 V ± 5% VPP high voltage input to perform the
Flasherase and Flashrite algorithms.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to VCC +1 V.
The Am28F010 is byte programmable using 10 ms pro-
gramming pulses in accordance with AMD’s Flashrite
programming algorithm. The typical room temperature
programming time of the Am28F010 is two seconds.
The entire chip is bulk erased using 10 ms erase pulses
according to AMD’s Flasherase alrogithm. Typical era-
sure at room temperature is accomplished in less than
one second. The windowed package and the 15–20
Publication# 11559 Rev: H Amendment/+2
Issue Date: January 1998
1 page  
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM28F010 -70
J
CB
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am28F010
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
AM28F010-70
AM28F010-90
AM28F010-120
AM28F010-150
AM28F010-200
Valid Combinations
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am28F010
5
5 Page 
FLASHERASE ERASE SEQUENCE
Erase Setup
Erase Setup is the first of a two-cycle erase command.
It is a command-only operation that stages the device
for bulk chip erase. The array contents are not altered
with this command. 20h is written to the command reg-
ister in order to perform the Erase Setup operation.
Erase
The second two-cycle erase command initiates the
bulk erase operation. You must write the Erase com-
mand (20h) again to the register. The erase operation
begins with the rising edge of the WE# pulse. The
erase operation must be terminated by writing a new
command (Erase-verify) to the register.
This two step sequence of the Setup and Erase com-
mands helps to ensure that memory contents are not
accidentally erased. Also, chip erasure can only occur
when high voltage is applied to the VPP pin and all con-
trol pins are in their proper state. In absence of this high
voltage, memory contents cannot be altered. Refer to
AC Erase Characteristics and Waveforms for specific
timing parameters.
Note: The Flash memory device must be fully
programmed to 00h data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable erasure.
Erase-Verify Command
The erase operation erases all bytes of the array
in parallel. After the erase operation, all bytes must be
sequentially verified. The Erase-verify operation is initi-
ated by writing A0h to the register. The byte address to
be verified must be supplied with the command. Ad-
dresses are latched on the falling edge of the WE#
pulse or CE# pulse, whichever occurs later. The rising
edge of the WE# pulse terminates the erase operation.
Margin Verify
During the Erase-verify operation, the device applies
an internally generated margin voltage to the
addressed byte. Reading FFh from the addressed byte
indicates that all bits in the byte are properly erased.
Verify Next Address
You must write the Erase-verify command with the ap-
propriate address to the register prior to verification of
each address. Each new address is latched on the fall-
ing edge of WE# or CE# pulse, whichever occurs later.
The process continues for each byte in the memory
array until a byte does not return FFh data or all the
bytes in the array are accessed and verified.
If an address is not verified to FFh data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verification then resumes at the address that failed to
verify. Erase is complete when all bytes in the array
have been verified. The device is now ready to be pro-
grammed. At this point, the verification operation is ter-
minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase electrical erase algorithm, illustrate how
commands and bus operations are combined to per-
form electrical erasure. Refer to AC Erase Characteris-
tics and Waveforms for specific timing parameters.
Am28F010
11
11 Page | ||
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| PDF Descargar | [ Datasheet AM27F010-70FE.PDF ] | |
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