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PDF AM27C4096-90DIB Data sheet ( Hoja de datos )
| Número de pieza | AM27C4096-90DIB | |
| Descripción | 512 Kilobit (64 K x 8-Bit) CMOS EPROM | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
Am27C512
512 Kilobit (64 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time
— Speed options as fast as 55 ns
s Low power consumption
— 20 µA typical CMOS standby current
s JEDEC-approved pinout
s Single +5 V power supply
s ±10% power supply tolerance standard
s 100% Flashrite™ programming
— Typical programming time of 8 seconds
s Latch-up protected to 100 mA from –1 V to
VCC + 1 V
s High noise immunity
s Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
s Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C512 is a 512-Kbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 64K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 8 seconds.
BLOCK DIAGRAM
OE#/VPP
CE#
A0–A15
Address
Inputs
VCC
VSS
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
524,288
Bit Cell
Matrix
08140I-1
Publication# 08140 Rev: I Amendment/0
Issue Date: May 1998
1 page  
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light
source. A dosage of 15 W seconds/cm2 is required to
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source, and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The device enters the programming mode when 12.75
V ± 0.25 V is applied to the OE#/VPP pin, and CE# is at
VIL.
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data pins.
The flowchart in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMD’s Flashrite algorithm. The Flashrite algo-
rithm reduces programming time by using a 100 µs pro-
gramming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad-
dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while se-
quencing through each address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at VCC = VPP =
5.25 V.
Please refer to Section 5 of the EPROM Products Data
Book for additional programming information and spec-
ifications.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level
program pulse applied to one device’s CE# input with
OE#/VPP = 12.75 V ± 0.25 V, will program that particu-
lar device. A high-level CE# input inhibits the other de-
vices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE#/VPP and CE#
at VIL, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gramming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#/VPP) must be driven low. CE#
controls the power to the device and is typically used to
select the device. OE#/VPP enables the device to out-
put data, independent of device selection. Addresses
must be stable for at least tACC–tOE. Refer to the
Switching Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
s Low memory power dissipation, and
s Assurance that output bus contention will not occur.
CE# should be decoded and used as the primary de-
vice-selecting function, while OE#/VPP be made a com-
Am27C512
5
5 Page 
PHYSICAL DIMENSIONS*
CDV028—28-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
INDEX AND
TERMINAL NO. 1
I.D. AREA
1
UV Lens
.565
.605
TOP VIEW
1.435
1.490
BASE PLANE
SEATING PLANE
.005 MIN
.045
.065
.014
.026
.015
.060
.100 BSC
SIDE VIEW
DATUM D
CENTER PLANE
.160
.220
.125
.200
.300 BSC
* For reference only. BSC is an ANSI standard for Basic Space Centering.
.700
MAX
94°
105°
.600
BSC
.008
.018
END VIEW
16-000038H-3
CDV028
DF10
3-30-95 ae
PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)
1.440
1.480
28 15
.600
.625
Pin 1 I.D.
.045
.065
.140
.225
.530
.580
14
.005 MIN
.630
.700
0°
10°
.008
.015
.120 .090
.160 .110
.014
.022
SEATING PLANE
.015
.060
16-038-SB-AG
PD 028
DG75
7-13-95 ae
Am27C512
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AM27C4096-90DIB.PDF ] | |
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