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PDF ALD500RAU-10PE Data sheet ( Hoja de datos )
| Número de pieza | ALD500RAU-10PE | |
| Descripción | PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE | |
| Fabricantes | Advanced Linear Devices | |
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ADVANCED
LINEAR
DEVICES, INC.
ALD500RAU/ALD500RA/ALD500R
PRECISION INTEGRATING ANALOG PROCESSOR
WITH PRECISION VOLTAGE REFERENCE
APPLICATIONS
• 4 1/2 digits to 5 1/2 digits plus sign measurements
• Precision analog signal processor
• Precision sensor interface
• High accuracy DC measurement functions
• Portable battery operated instruments
• Computer peripheral
• PCMCIA
FEATURES
• Resolution up to 18 bits plus sign bit and over-range bit
• Accuracy independent of input source impedances
• Accurate on-chip voltage reference
• Tempco as low as 10 ppm/°C guaranteed
• Chip select - power down mode
• High input impedance of 1012 Ω
• Inherently filters and integrates any external noise spikes
• Differential analog input
• Wide bipolar analog input voltage range ±3.5V
• Automatic zero offset compensation
• Low linearity error - as low as 0.001% typical
• Fast zero-crossing comparator - 1µs
• Low power dissipation - 6mW typical
• Automatic internal polarity detection
• Low input current - 2pA typical
• Optional digital control from a microcontroller, an ASIC, or
a dedicated digital circuit
• Flexible conversion speed vs. resolution trade-off
BENEFITS
• Low cost, simple functionality
• Wide dynamic signal range
• Very high noise immunity
• Automatic compensation and cancellation
of error sources
• Easy to use to acquire bipolar signals
• Up to 19 bit (18 bit + sign bit) single conversion
or 21 bit (20 bit + sign bit) multiple conversion
and noise performance
• Inherently linear and stable with temperature
and component variations
PIN CONFIGURATION
ALD500R
IB 1
CINT 2
V- 3
CAZ 4
BUF 5
AGND
C-REF
C+REF
N/C
6
7
8
9
N/C 10
20 CS
19 V+
18 DGND
17 COUT
16 B
15 A
14 V+IN
13 V-IN
12 V+REF
11 V-REF
QE, PE, SE PACKAGE
* N/C pin is connected internally. Connect to V-.
Ordering Information
Resolution Endpoint Voltage Reference
Linearity Accuracy/Tempco
20L PDIP
16 bit 0.015% 0.5% 50ppm/C ALD500R-50PE
Package Type
20L SOIC
ALD500R-50SE
20L QSOP
ALD500R-50QE
20LCDIP
Operating
Temperature
0°C to 70°C
17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PE ALD500RA-20SE ALD500RA-20QE
0°C to 70°C
18 bit 0.005%
ALD500RAU-20PE ALD500RAU-20SE ALD500RAU-20QE
17 bit 0.01% 0.2% 10ppm/C ALD500RA-10PE ALD500RA-10SE ALD500RA-10QE
0°C to 70°C
18 bit 0.005%
ALD500RAU-10PE ALD500RAU-10SE ALD500RAU-10QE
17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PEI ALD500RA-20SEI ALD500RA-20QEI
-40°C to +85°C
18 bit 0.005%
ALD500RAU-20PEI ALD500RAU-20SEI ALD500RAU-20QEI
18 bit 0.005% 0.3% 20ppm/C
ALD500RAU-20DE -55°C to +125°C
* Contact factory for customized voltage reference voltage levels, accuracy and tempco specifications.
Rev. 1.01 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155, Fax: (408) 747-1286
http://www.aldinc.com
1 page  
DC & AC ELECTRICAL CHARACTERISTICS
TA = 25°C V supply = ±5.0V unless otherwise specified; CAZ = CREF = 0.47µf
Parameter
Supply Current
500RAU
500RA
500R
Symbol Min Typ Max Min Typ Max Min Typ Max
Unit
Test Conditions
IS
0.6 1.0
0.6 1.0
0.6 1.0 mA
V+ = 5V , A =1,B=1
Power Dissipation
PD
10 10
10 mW V supply= ±5V
Positive Supply Range V+S
4.5
5.5 4.5
5.5 4.5
5.5 V
Note 4
Negative Supply Range V-S
-4.5
-5.5 -4.5
-5.5 -4.5
-5.5 V
Note 4
Comparator Logic 1,
Output High
Comparator Logic 0,
Output Low
Logic 1, Input High
Voltage
Logic 0, Input Low
Voltage
Logic Input Current
Comparator Delay
VOH
4
4
4 V ISOURCE = 400µA
VOL
0.4 0.4
0.4 V
ISINK = 1.1mA
VIH 3.5
3.5
3.5
V
VIL
11
1V
IL 0.01
tD 1
0.01
1
0.01 µA
1 µsec Note 5
Figure 3. ALD500R TIMING DIAGRAM
1 Conversion Cycle
1.8432 MHz Clock
A INPUT
B INPUT
123,093
Clock Pulses
0.5416 µs
66.667 msec.
123,093
Clock Pulses
66.667 msec.
COUT
Positive Input Signal
NOT VALID
COUT
Negative Input Signal
NOT VALID
Auto Zero
Phase
Input Signal
Integration
Phase
START
CONVERSION
CYCLE
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed number
of clock pulses
by design.
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
Reference
Voltage
Deintegration
Phase
Variable
number of
clock pulses.
At VIN MAX,
max. number of
clock pulses
=~ 246,185
Integrator Zero
Phase
Auto Zero
Phase
Fixed period of
approx.1 msec.
Stop counter upon
detection of comparator
output going from high
to low state.
REPEAT
CONVERSION
CYCLE
START INTEGRATOR ZERO CYCLE
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
5
5 Page 
EQUATIONS AND DERIVATIONS
Dual Slope Analog Processor equations and derivations
are as follows:
∫1
RINT . CINT
tINT
0
VIN(t)dt
=
VREF
RINT
.
.
tDINT
CINT
(1)
For VIN(t) = VIN (constant):
1
RINT .
CINT
tINT
.
VIN
=
VREF
RINT
.
.
tDINT
CINT
(2)
... VIN = VREF .
tDINT
tINT
CINT =
tINT . IB
VINT
(2a)
(3)
At VINMAX, the current IB is also at a maximum level,
for a given RINT value:
RINT =
VIN
IB
=
VINMAX
IBMAX
(4)
From equation (2a),
VREF =
VIN . tINT
tDINT
OR
VREF = VIN MAX . tINT
tDINT MAX
Rearranging equations (3) and (4):
tINT =
and
CINT . VINT
IB
IBMAX =
VINMAX
RINT
At VINT = VINT MAX, equation (6) becomes:
tINT = CINT . VINTMAX
IBMAX
(5a)
(5b)
(6)
(7)
(6a)
Combining (6a) and (7):
... tINT = CINT . VINTMAX . RINT
VINMAX
(8)
In equation (5b), substituting equation (8) for tINT:
CINT . VINTMAX . RINT
VREF =
VIN MAX .
VIN MAX
tDINT MAX
= CINT . VINTMAX . RINT
tDINT MAX
(9)
For tDINT MAX = 2 x tINT,
equation (9) becomes:
VREF =
CINT . VINTMAX . RINT
2tINT
(10)
DESIGN EXAMPLES
We now apply these equations in the following
design examples.
Design Example 1:
1. Pick resolution = 16 bit.
2.
Pick
tINT
=
4x
1
60Hz
= 4 x 16.6667 msec.
= 66.6667ms
= 0.0666667 sec.
3. Pick clock period = 1.08507 µs and number of counts
over tINT = 0.0666667 = 61440
1.08507x10-6
4. Pick VINMAX value, e.g., VINMAX = 2.0 V
I BMAX = 20µA
RINT
=
2.0
20x10-6
=
100
kΩ
5. Applying equation (3) to calculate CINT:
CINT = (0.0666667)(20x10-6)/4 where VINT = 4.0V
~= 0.33 µF
6. Pick CREF and CAZ ≥ CINT: CREF ~=CAZ ~= 0.33 µF
7. Pick tDINT = 2 x tINT = 133.3333 msec
8. Calculate VREF =
VINTMAX . CINT . RINT
tDINT MAX
V
= 4 x 0.33 x 10-6 x 100 x 103 V
133.3333 x 10-3
=~ 1.00V
Design Example 2:
1. Select resolution of 17 bit. Total number of
counts during tINT is131,072.
2. We can pick tINT of 16.6667 msec. x 5 = 83.3333 msec.
or alternately, pick t INT equal
16.6667 msec. x 6 = 100.00 msec.
(for 60 Hz rejection)
which is t INT = 20.00 msec. x 5
= 100.00 msec. (for 50 Hz rejection)
Therefore, using t INT = 100 msec. would achieve
both 50 Hz and 60 Hz cycle noise rejection. For this
example, the following calculations would assume
t INT of 100 msec. Now select period equal to
0.5425 µsec. (clock frequency of 1.8432 MHz)
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
11
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| PDF Descargar | [ Datasheet ALD500RAU-10PE.PDF ] | |
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