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PDF AT27BV512-12JC Data sheet ( Hoja de datos )
| Número de pieza | AT27BV512-12JC | |
| Descripción | 512K 64K x 8 Unregulated Battery-Voltage High Speed OTP CMOS EPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT27BV512
Features
Fast Read Access Time - 90 ns
•• Dual Voltage Range Operation
Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V ± 10% Supply Range
Pin Compatible with JEDEC Standard AT27C512
•• Low Power CMOS Operation
20 µA max. (less than 1µA typical) Standby for VCC = 3.6V
• 29 mW max. Active at 5 MHz for VCC = 3.6V
JEDEC Standard Surface Mount Packages
32-Lead PLCC
28-Lead 330-mil SOIC
28-Lead TSOP
• High Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
• Rapid™ Programming Algorithm - 100 µs/byte (typical)
• CMOS and TTL Compatible Inputs and Outputs
JEDEC Standard for LVTTL and LVBO
Integrated Product Identification Code
•• Commercial and Industrial Temperature Ranges
Description
The AT27BV512 is a high performance, low power, low voltage 524,288 bit one-time
programmable read only memory (OTP EPROM) organized as 64K by 8 bits. It re-
quires only one supply in the range of 2.7V to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using either regulated or unregulated battery
power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 2.7V, any byte can be
accessed in less than 90 ns. With a typical power consumption of only 18 mW at 5
MHz and VCC = 3V, the AT27BV512 consumes less than one fifth the power of a
standard 5V EPROM.
Pin Configurations
SOIC Top View
(continued)
Pin Name
A0 - A15
O0 - O7
CE
OE/VPP
NC
Function
Addresses
Outputs
Chip Enable
Output Enable
No Connect
PLCC Top View
512K (64K x 8)
Unregulated
Battery-Voltage™
High Speed
OTP
CMOS EPROM
AT27BV512
TSOP Top View
Type 1
Note: PLCC Package Pins 1 and
17 are DON’T CONNECT.
0602A
3-13
1 page  
AT27BV512
AC Characteristics for Read Operation (VCC = 2.7V to 3.6V and 4.5V to 5.5V)
AT27BV512
-90 -12 -15
Symbol
tACC (3)
tCE (2)
tOE (2, 3)
tDF (4, 5)
tOH
Parameter
Condition
Address to Output Delay
CE = OE/VPP = VIL
CE to Output Delay
OE/VPP = VIL
OE/VPP to Output Delay
CE = VIL
OE/VPP or CE High to Output Float,
whichever occurred first
Output Hold from Address, CE or
OE/VPP, whichever occurred first
Min Max
90
90
50
40
0
Min Max Min Max Units
120 150 ns
120 150 ns
50 60 ns
40 50 ns
0 0 ns
Notes: 2, 3, 4, 5. - see AC Waveforms for Read Operation.
AC Waveforms for Read Operation (1)
Notes: 1. Timing measurement references are 0.8V and 2.0V.
Input AC drive levels are 0.45V and 2.4V, unless
otherwise specified.
2. OE/VPP may be delayed up to tCE - tOE after the
falling edge of CE without impact on tCE.
3. OE/VPP may be delayed up to tACC - tOE after the
address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer
driven.
6. When reading the 27BV512, a 0.1 µF capacitor is required
across VCC and grond to supress spurious voltage transients.
3-17
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AT27BV512-12JC.PDF ] | |
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