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AT25256-10CIのメーカーはATMEL Corporationです、この部品の機能は「SPI Serial EEPROMs」です。 |
部品番号 | AT25256-10CI |
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部品説明 | SPI Serial EEPROMs | ||
メーカ | ATMEL Corporation | ||
ロゴ | |||
このページの下部にプレビューとAT25256-10CIダウンロード(pdfファイル)リンクがあります。 Total 17 pages
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• 3 MHz Clock Rate
• 64-Byte Page Mode and Byte Write Operation
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-Timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years
– ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP,
and 8-Pin Leadless Array Packages
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low power and low voltage operation are essential. The devices are available in
Pin Configurations
(continued)
Pin Name Function
14-Lead TSSOP
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
DC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
Don't Connect
CS
SO
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
16-Pin SOIC
CS
SO
NC
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
8
16 VCC
15 HOLD
14 NC
13 NC
12 NC
11 NC
10 SCK
9 SI
20-Lead TSSOP*
NC
CS
SO
SO
NC
NC
WP
GND
DC
NC
1
2
3
4
5
6
7
8
9
10
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 DC
11 NC
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128
AT25256
8-Pin PDIP
8-Pin SOIC
8-Pin Leadless Array
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
Rev. 0872E–08/98
1
1 Page AT25128/256
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions
Max Units
Conditions
COUT
CIN
Note:
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
8 pF
6 pF
VOUT = 0V
VIN = 0V
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V(unless otherwise noted).
Symbol Parameter
Test Condition
Min Typ
VCC1
VCC2
VCC3
ICC1
ICC2
ISB1
ISB2
ISB3
IIL
IOL
VIL(1)
VIH(1)
VOL1
VOH1
VOL2
VOH2
Note:
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
VCC = 5.0V at 1 MHz, SO = Open, Read
VCC = 5.0V at 2 MHz, SO = Open, Read, Write
VCC = 1.8V, CS = VCC
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
VIN = 0V to VCC, TAC = 0°C to 70°C
Input High Voltage
Output Low Voltage
Output High Voltage
4.5 ≤ VCC ≤ 5.5V
IOL = 3.0 mA
IOH = -1.6 mA
Output Low Voltage
Output High Voltage
1.8V≤ VCC ≤3.6V
IOL = 0.15mA
IOH = -100µA
1. VIL and VIH max are reference only and are not tested.
1.8
2.7
4.5
-3.0
-3.0
-1.0
VCC x 0.7
vCC - 0.8
VCC - 0.2
2.0
3.0
0.1
0.2
2.0
Max
3.6
5.5
5.5
3.0
5.0
2.0
2.0
5.0
3.0
3.0
VCC x 0.3
VCC + 0.5
0.4
0.2
Units
V
V
V
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
3
3Pages Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an
input, the AT25128/256 always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128/256 has
separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no
data will be shifted into the AT25128/256, and the serial
output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize
the serial communication.
CHIP SELECT: The AT25128/256 is selected when the CS
pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS
pin to select the AT25128/256. When the device is selected
and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device
without resetting the serial sequence. To pause, the HOLD
pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status regis-
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the
status register. The WP pin function is blocked when the
WPEN bit in the status register is “0”. This will allow the
user to install the AT25128/256 in a system with the WP pin
tied to ground and still be able to write to the status regis-
ter. All WP pin functions are enabled when the WPEN bit is
set to “1”.
SPI Serial Interface
AT25128/256
6 AT25128/256
6 Page | |||
ページ | 合計 : 17 ページ | ||
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