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Datasheet AT17N512-10CC PDF ( 特性, スペック, ピン接続図 )

部品番号 AT17N512-10CC
部品説明 FPGA Configuration Memory
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 
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AT17N512-10CC Datasheet, AT17N512-10CC PDF,ピン配置, 機能
Features
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
Available as a 3.3V (±10%) Commercial and Industrial Version
Simple Interface to SRAM FPGAs
Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
Mode
Very Low-power CMOS EEPROM Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
Low-power Standby Mode
High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8-lead LAP
Yes
Yes –
8-lead PDIP
8-lead SOIC
Yes Yes
Yes Use 8-lead LAP(1) Use 8-lead LAP(1)
20-lead SOIC
Yes
Yes
Yes –
44-lead TQFP
Yes Yes
Note:
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
Rev. 3020A–CNFG–05/03
1

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AT17N512-10CC pdf, ピン配列
AT17N256/512/010/002/040
44 TQFP
NC 1
NC 2
NC 3
NC 4
NC 5
NC 6
DC 7
NC 8
NC 9
NC 10
NC 11
33 NC
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 NC
23 DC
3020A–CNFG–04/10/03
3


3Pages


AT17N512-10CC 電子部品, 半導体
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17N
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the master serial mode configuration of Atmel AT17N series
configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL
OTP PROMs.
Control of
Configuration
Most connections between the FPGA device and the AT17N Serial EEPROM are simple
and self-explanatory.
• The DATA output of the AT17N series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17N series
configurator.
• SER_EN must be connected to VCC (except during ISP).
• The CE and OE/Reset are driven by the FPGA to enable output data buffer of the
EEPROM.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the chip.
Standby Mode
The AT17N series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of
current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040).
6 AT17N256/512/010/002/040
3020A–CNFG–04/10/03

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