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PDF AT17N256 Data sheet ( Hoja de datos )
| Número de pieza | AT17N256 | |
| Descripción | FPGA Configuration Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
• Available as a 3.3V (±10%) Commercial and Industrial Version
• Simple Interface to SRAM FPGAs
• Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
• Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
Mode
• Very Low-power CMOS EEPROM Process
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
• Low-power Standby Mode
• High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8-lead LAP
–
Yes
Yes –
8-lead PDIP
8-lead SOIC
Yes Yes
–
Yes Use 8-lead LAP(1) Use 8-lead LAP(1)
–
–
20-lead SOIC
Yes
Yes
Yes –
44-lead TQFP
–
–
Yes Yes
Note:
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
Rev. 3020A–CNFG–05/03
1
1 page  
AT17N256/512/010/002/040
Pin Description
Name
DATA
CLK
RESET/OE
CE
GND
DC
DC
VCC(SER_EN)
VCC
DATA
I/O
I/O
I
I
I
O
O
I
CLK
RESET/OE
CE
GND
VCC(SER_EN)
VCC
NC
DC
AT17N256
8
DIP/
SOIC
20
SOIC
11
23
38
4 10
5 11
6 13
––
7 18
8 20
AT17N512/
AT17N010
8
DIP/
LAP
20
SOIC
11
23
38
4 10
5 11
6 13
––
7 18
8 20
AT17N002
AT17N040
8
LAP
1
2
3
4
5
6
–
7
8
20
SOIC
1
3
8
10
11
13
–
18
20
44
TQFP
40
43
13
15
18
21
23
35
38
44
TQFP
40
43
13
15
18
21
23
35
38
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
3.3V (±10%) Commercial and Industrial power supply pin.
NC pins are No Connect pins, which are not internally bonded out to the die.
DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
3020A–CNFG–04/10/03
5
5 Page 
AT17N256/512/010/002/040
Figure 1. Ordering Code
AT17N256-10PC
Voltage
3.3V +-10%
Size (Bits)
256 = 256K
512 = 512K
010 = 1M
002 = 2M
040 = 4M
Package
C = 8CN4
P = 8P3
N = 8S1
S = 20S2
TQ = 44A
Temperature
C = Commercial
I = Industrial
8CN4
8P3
8S1
20S2
44A
Package Type
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
3020A–CNFG–04/10/03
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AT17N256.PDF ] | |
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