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Note 1.
AT17LV65A, AT17LV128A,
and AT17LV256A are
Not Recommended for New
Designs (NRND) and are
Replaced by AT17LV512A.
AT17LV65A(1), AT17LV128A(1), AT17LV256A(1)
AT17LV512A, AT17LV010A, AT17LV002A
FPGA Configuration EEPROM Memory
3.3V and 5V System Support
Features
DATASHEET
 EE Programmable Serial Memories Designed to Store Configuration Programs for
Altera® FLEX® and APEX™ Field Programmable Gate Arrays (FPGA)
̶ 65,536 x 1-bit(1)
̶ 262,144 x 1-bit(1)
̶ 1,048,576 x 1-bit
̶ 131,072 x 1-bit(1)
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
 Supports both 3.3V and 5.0V Operating Voltage Applications
 In-System Programmable (ISP) via 2-wire Bus
 Simple Interface to SRAM FPGAs
 Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera FLEX,
APEX Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®,
Virtex™ FPGAs, Motorola MPA1000 FPGAs
 Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
 Very Low-power CMOS EEPROM Process
 Programmable Reset Polarity
 8-lead PDIP and 20-lead PLCC Packages (Pin-compatible Across Product Family)
 Emulation of the Atmel AT24C Serial EEPROMs
 Low-power Standby Mode
 High-reliability
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
 Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The Atmel® AT17LVxxxA FPGA configuration EEPROMs (Configurators) provide an
easy-to-use, cost-effective configuration memory solution for FPGAs. The
AT17LVxxxA are packaged in 8-lead PDIP and 20-lead PLCC options. The
AT17LVxxxA configurator uses a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function by
programming four EEPROM bytes. These devices support a write protection
mechanism within its programming mode.
The AT17LVxxxA configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP
Cable.
Table 1. AT17LVxxxA Packages
Package
8-lead PDIP
20-lead PLCC
AT17LV512A
Yes
Yes
AT17LV010A
Yes
Yes
AT17LV002A
–
Yes
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014

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Table 1-2.
Name
DATA
Pin Configurations
AT17LV65A/128A/256A(2)
I/O 20-lead PLCC
I/O 2
DCLK
I
4
WP1
I
–
RESET/OE
I
8
nCS I
9
GND
nCASC(1)
A2
O
I
10
12
READY
O
–
AT17LV512A/010A
8-lead PDIP
20-lead PLCC
12
24
–5
38
49
5 10
6 12
– 15
AT17LV002A
20-lead PLCC
2
4
5
8
9
10
12
15
SER_EN
I
18
7 18 18
VCC 20 8 20
Notes: 1. The nCASC feature is not available on the AT17LV65A (NRND) device.
2. The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
20
Figure 1-1. Pinouts(1)
8-lead PDIP
(Top View)
DATA
DCLK
(WP(2)) RESET/OE
nCS
1
2
3
4
8 VCC
7 SER_EN
6 nCASC(4) (A2)
5 GND
20-lead PLCC
(Top View)
DCLK
WP1(3)
NC
NC
(WP(2)) RESET/OE
4
5
6
7
8
18 SER_EN
17 NC
16 NC
15 NC (READY(3))
14 NC
Notes:
1. Drawings are not to scale.
2. This pin is only available on the AT17LV65A/128A/256A (NRND).
3. This pin is only available on the AT17LV512A/010A/002A.
4. The nCASC feature is not available on the AT17LV65A (NRND).
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
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6. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the next clock signal to the configurator asserts its nCASC
output low and disables its DATA line driver. The second configurator recognizes the low level on its nCS input
and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to a Low level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to a High
level.
The AT17LV65A (NRND) does not have the nCASC feature to perform cascaded configurations.
7. AT17LVxxxA Reset Polarity
The AT17LVxxxA configurator allows the user to program the polarity of the RESET/OE pin as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms.
8. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated
inside the chip.
9. Standby Mode
The AT17LVxxxA enters a low-power standby mode whenever nCS is asserted High. In this mode,
the configurator consumes less than 150μA of current at 3.3V. The output remains in a high-impedance state
regardless of the state of the RESET/OE input.
6 AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014

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