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AT17LV040 の電気的特性と機能

AT17LV040のメーカーはATMEL Corporationです、この部品の機能は「FPGA Configuration EEPROM Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT17LV040
部品説明 FPGA Configuration EEPROM Memory
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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AT17LV040 Datasheet, AT17LV040 PDF,ピン配置, 機能
Note 1.
AT17LV65 and AT17LV128
are Not Recommended for
New Designs (NRND) and
are Replaced by AT17LV256.
AT17LV65(1), AT17LV128(1), AT17LV256,
AT17LV512, AT17LV010, AT17LV002, AT17LV040
FPGA Configuration EEPROM Memory
3.3V and 5.0V System Support
Features
DATASHEET
EE Programmable Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
̶ 65,536 x 1-bit(1)
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
̶ 131,072 x 1-bit(1)
̶ 1,048,576 x 1-bit
̶ 4,194,304 x 1-bit
̶ 262,144 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®
FLEX®, APEXDevices, ORCA®, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC
Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and
44-lead TQFP Packages
Emulation of the Atmel AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory solution for Field Programmable Gate
Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead
SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The
AT17LV Configurators use a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function during
programming. These devices also support a write protection mechanism within its
programming mode.
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

1 Page





AT17LV040 pdf, ピン配列
1. Pin Configuration and Descriptions
Table 1-1. Pin Descriptions
Pin
DATA
CLK
WP1
RESET/OE
WP
WP2
CE
Description
Three-state Data Output for Configuration. Open-collector bi-directional pin for
programming.
Clock Input. Used to increment the internal address and bit counter for reading and
programming.
Write Protect (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
Write Protect Input (when CE is Low) during programming only (SER_EN Low). When WP is
Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on the AT17LV65 (NRND),
AT17LV128 (NRND), and the AT17LV256.
Write Protect (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on the AT17LV512/010.
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
Low).
GND
CEO
A2
READY
SER_EN
VCC
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (Active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV devices, the CEO pin of one device
must be connected to the CE input of the next device in the chain. It will stay Low as long as
CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again. This CEO feature is not available on the
AT17LV65 (NRND).
Device Selection Input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
Open Collector Reset State Indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7kpull-up resistor when this pin is used.
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC.
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
3


3Pages


AT17LV040 電子部品, 半導体
2. Block Diagram
Figure 2-1. Block Diagram
SER_EN
WP1(2)
WP2(2)
Programming
Mode Logic
Programming
Data Shift
Register
Power On
Reset
Row Decoder
EEPROM
Cell Matrix
Column Decoder
TC
CLK READY(2) REST/OE (WP(1))
CE CEO(3) (A2)
DATA
Notes: 1. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
2. This pin is only available on AT17LV512, AT17LV010, and AT17LV002.
3. The CEO feature is not available on the AT17LV65 (NRND).
6 AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

6 Page



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部品番号部品説明メーカ
AT17LV040

FPGA Configuration EEPROM Memory

ATMEL Corporation
ATMEL Corporation


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