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PDF CT2577 Data sheet ( Hoja de datos )
| Número de pieza | CT2577 | |
| Descripción | APPLICATION NOTE #108 | |
| Fabricantes | Aeroflex Circuit Technology | |
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35 South Service Road · Plainview, NY 11803
TEL: 516 694-6700 · FAX: 516 694-6715
The Future in Microelectronics
CIRCUIT TECHNOLOGY
APPLICATION NOTE #108
CT2577 / 79
SmaRT Series
Users Guide
Point of Contact:
John Vanchieri
Tel: (516) 752-2484
APPLICATION NOTE #108
1
Released 9/98
1 page  
DATA0-15
16 bit bidirectional data highway access to internal RAM and registers. When in 8 bit
mode only DATA 0-7 are used. Data inputs / outputs are inverted when the Multibus
interface is selected.
NACK
After a write / read cycle has begun, this signal indicates that the write / read
operation to the unit has been acknowledged and that access has been granted.
Read data is available and write data is complete. The user can complete the write /
read cycle.
“0" = Cycle is acknowledged, access granted.
“1" = No acknowledge, wait.
NEMPTY
Empty flag for the Command / Status FIFO memory which can store up to 32
command words (RT) or 32 status words (BC). In RT mode the memory will store all
command words that have accessed the main RAM. This includes all standard
commands to receive and transmit data from the main RAM and mode codes with
data that require subsystem involvement ie. Synchronize With Data and Transmit
Vector Word. In BC mode all status responses are stored in this memory. Access to
this memory is gained by reading from address 0 00 00.
"0" output to this pin means the FIFO is empty (no words).
"1" output to this pin means the FIFO is NOT empty (has words to be read).
NFULL
Full flag for the Command / Status FIFO memory. When the signal goes low the
memoryis full and will not store any more data.
NRES
Bidirectional reset pin. Interface to this pin should be in the form of an open collector
pull down driver. The unit will be reset when a low level input is asserted on power up.
The pin is bidirectional in that the unit will drive the signal out low after the status
response of the mode code Reset Remote Terminal. Upon reset the unit will initialise
to RT mode and will be able to respond immediately after the rising edge of NRES.
T0-15
16 bit bidirectional data highway access to internal RAM and registers. When in 8 bit
mode only DATA 0-7 are used. Data inputs / outputs are inverted when the Multibus
interface is selected. Allows the user to have access to the MIL-STD-1553 bus traffic
in real time. The user can utilize this bus for message illegalization and read words
such as Synch w/Data directly off the T0-15 bus. Utilizing NDATA signal, the user can
read the data words off the T0-15 bus as the DMA burst is transferring the data into
RAM.
UB Upper byte: When the unit is in 8 bit mode this signal is used as the LSB of the
address lines. In 16 bit mode the signal is not used and the LSB of the address lines
is ADIN 0.
NRD
VME Mode Data Strobe for a data transfer
0 = Read/Write data
1 = Tri-state the Data 0-15 bus
Multibus Mode:Read strobe for a data transfer
0 = Read data FROM the unit TO the Subsystem
1 = Tri-state the Data0-15 bus
NWR
VME Mode Read/Write direction flag for a NRD data strobe
0 = Write data FROM Subsystem TO the Device
1 = Read data FROM Device unit TO the Subsystem
APPLICATION NOTE #108
5
Released 9/98
5 Page 
/ writes and store them in the buffer instead. The user accesses the same locations as if they
would if they were directly accessing the main RAM.
The block transfer logic is enabled with signal NENBTL (pin A7) being active low and is not
applicable to subaddress 00 and 1F (unless McAir is selected) areas of ram. The block
transfer logic may also be configured by writing to certain address locations providing
NENBTL is selected, ie.
0 1 00 02
0 1 00 03
0 1 00 04
0 1 00 05
402h
403h
404h
405h
Disable Read
Disable Read
Enable Read
Enable Read
Disable Write
Enable Write
Disable Write
Enable Write
Reset will enable both Write and Read.
Note: All 257X versions with internal RAM that do not have NENBTL as a dsiscrete input
have it enabled internally.
READ (RECEIVE)
The Read BTL functions similarly to the Write BTL in that the BTL buffers the read activity. A
subsystem read will initially generate a DMA of that entire portion of the subaddress to be
stored in the BTL buffer. The subsystem can then read out the data at its leisure while the
main RAM is free for future updates. Since the entire portion of the subaddress data was
DMA from the RAM, the data read from the BTL buffer is guaranteed contiguous.
The user must read data from the device in a specific sequence starting with the first word
received in the n-1 location and ending with the last word received in location 00 of the
subaddress. The BTL will sense the read from location 00 and reset the sequence ready for
a new access.
1. The first word of a received message will be read first, this will initiate a burst DMA
transfer of a complete message from main memory to the 32 word BTL buffer memory,
during which time the subsystem will be locked out. Data is transferred at the rate of 250
ns per word.
2. The sub system can then read data from the ram at its leisure. The last word to be read
will be the last word received in the message and read from location zero. This will reset
the block transfer logic.
3. If the 1553 DMA transfer to the main RAM becomes active during the burst transfer, the
transfer will complete and then be locked out until the 1553 is complete. However the 32
word BTL buffer memory will be accessible to the subsystem at this time to read out the
data.
4. If the 1553 DMA transfer to the main RAM becomes active before the start of the burst
transfer, the transfer will belocked out until the 1553 is complete. The sub system will be
locked out during this time (main ram being accessed by the 1553 and the 32 word buffer
memory is waiting for the receive message). When the 1553 is complete the burst
transfer will take place and then unlock the subsystem.
APPLICATION NOTE #108
11
Released 9/98
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CT2577.PDF ] | |
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