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PDF CS9210 Data sheet ( Hoja de datos )

Número de pieza CS9210
Descripción Geode CS9210 Graphics Companion DSTN Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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April 2000
Geode™ CS9210 Graphics Companion
DSTN Controller
General Description
The CS9210 graphics companion is suitable for systems
that use either the GXLV or GXm processor along with the
CS5530 I/O companion; all members of the National
Semiconductor® Geode™ family of products. The
CS9210 converts the digital RGB output stream to the dig-
ital graphics input stream required by most industry stan-
dard DSTN color flat panel LCDs. It can drive all standard
DSTN flat panels up to a 1024x768 resolution. The sys-
tem connection example shows how the CS9210 inter-
faces with the rest of the system components.
Features
 18-bit color support for digital pixel input
 65 MHz pixel clock operation supports up to 1024x768
panels
 Simultaneous CRT and DSTN display with up to 75 Hz
refresh rate
 2X display refresh modes, up to 120 Hz
 Supports most SVGA DSTN panels and the VESA
FPDI (Flat Panel Display Interface) Revision 1.0
Specification
 TFT panel support provided by use of one connector;
allows a pass-through mode for the digital pixel input
 Programmable frame rate modulation (FRM), up to 32
levels
 Programmable dither, up to 16 levels
 Supports EDO memory, 16-bit interface
 Configuration via a serial programming interface
 Low-power, 3.3V operation
 144-pin LQFP (Low-profile Quad Flat Pack)
Geode™ CS9210 System Connection Example
Pixel Data
18
Geode™
GXm
or
GXLV
Processor
Geode™
CS5530
I/O
Companion
Video Port (YUV)
Pixel Port 24
Serial
Configuration
4
Geode™
CS9210
Graphics
Companion
Addr Control 13
DRAM Data 16
Addr Control
DRAM Data
13
16
DRAM-A
256Kx16 bit
DRAM-B
256Kx16 bit
16 3
3
Control
Clocks
Panel Data
DSTN
LCD
LCD Power
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode is a trademark of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
www.national.com

1 page




CS9210 pdf
Signal Definitions (Continued)
VDD
VSS
FP_HSYNC
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
RED0
RED1
RED2
RED3
RED4
RED5
SCLK
SDIN
VDD
VSS
VSS
DOTCLK
SCS
SDO
MA_A9
MA_A8
MA_A7
MA_A6
MA_A5
MA_A4
MA_A3
MA_A2
MA_A1
MA_A0
MD_A15
MD_A14
MD_A13
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Geode™ CS9210
Graphics Companion
Top View
108 VDD
107 LD11
106 LD10
105 LD9
104 LD8
103 LD7
102 LD6
101 LD5
100 LD4
99 LD3
98 LD2
97 LD1
96 LD0
95 MA_B9
94 MA_B8
93 MA_B7
92 MA_B6
91 VDD
90 VSS
89 VSS
88 MA_B5
87 MA_B4
86 MA_B3
85 MA_B2
84 MA_B1
83 MA_B0
82 MD_B15
81 MD_B14
80 MD_B13
79 MD_B12
78 MD_B11
77 MD_B10
76 MD_B9
75 MD_B8
74 MD_B7
73 VDD
Figure 2-2. 144-Pin LQFP Pin Assignment Diagram
Order Number: CS9210-VNG
Revision 3.2
5 www.national.com

5 Page





CS9210 arduino
Signal Definitions (Continued)
2.2.4 Memory Interface Signals (Continued)
Signal Name
Pin No.
Type
(Drive) Description
LCASB#
WEA#
WEB#
61 O DRAM Bank B Low Byte Column Address Strobe
(4 mA) The column address strobe for the lower eight bits of data for Bank B
of the DRAM.
58 O DRAM Bank A Write Enable
(4 mA) The write enable signal for Bank A of the DRAM.
59 O DRAM Bank B Write Enable
(4 mA) The write enable signal for Bank B of the DRAM.
2.2.5 Reset and Internal Test Pins
Signal Name
Pin No.
Type
(Drive)
RESET#
132 I
TEST
124 I
Description
Reset
This pin is the system reset input.
Reserved
This pin must be tied to ground. It is a National Semiconductor internal
test mode pin only.
2.2.6 Power and Ground Pins
Signal Name
VDD
VSS
Pin No.
1, 17, 36,
37, 55,
72, 73,
91, 108,
125, 144
2, 18, 19,
38, 54,
71, 89,
90, 109,
126, 128
Type
(Drive)
PWR
GND
Description
Power Connection (total of 11 pins)
Power for the DRAM and system interface signals. These should be
supplied with 3.3V.
Ground Connection (total of 11 pins)
Ground connection.
Revision 3.2
11 www.national.com

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