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PDF A6277ELW Data sheet ( 特性 )

部品番号 A6277ELW
部品説明 8-BIT SERIAL-INPUT/ CONSTANTCURRENT LATCHED LED DRIVER
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A6277ELW Datasheet, A6277ELW PDF,ピン配置, 機能
6277
8-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
A6277ELW
LOGIC
GROUND
SERIAL
DATA IN
1
2
CLOCK 3 CK
LATCH
ENABLE
HIGH/LOW
(CURRENT)
POWER
GROUND
4
5
6
OUT 0 7
L
SUB
OUT1 8
OUT 2 9
OUT3 10
VDD 20
IO
REGULATOR
19
18
FF 17
OE 16
REGISTER
LATCHES
15
SUB
14
LOGIC
SUPPLY
REXT
SERIAL
DATA OUT1
SERIAL
DATA OUT2
OUTPUT
ENABLE
POWER
GROUND
OUT 7
13 OUT6
12 OUT5
11 OUT4
Dwg. PP-029-17A
Note that the A6277EA (DIP) and the A6277ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD ...................... 7.0 V
Output Voltage Range,
VO ............................ -0.5 V to +24 V
Output Current, IO ....................... 150 mA
Input Voltage Range,
VI .................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
PD ..................................... See Graph
Operating Temperature Range, TA
Suffix ‘S-’ ................ -20°C to +85°C
Suffix ‘E-’ ................ -40°C to +85°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still suscep-
tible to damage if exposed to extremely high
static electrical charges.
The A6277x is specifically designed for LED-display applications.
Each BiCMOS device includes an 8-bit CMOS shift register, accompa-
nying data latches, and eight npn constant-current sink drivers. Two
package styles and two operating temperature ranges are available.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is deter-
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. In addition, a HIGH/LOW function
enables full selected current with the application of a logic low, or 50%
selected current with the application of a logic high.
The first character of the part number suffix determines the device
operating temperature range. Suffix ‘E–’ is for -40°C to +85°C, and
suffix ‘S–’ is -20°C to +85°C. Two package styles are provided for
through-hole DIP (suffix ‘–A’) or surface-mount SOIC (suffix ‘–LW’)
applications. The copper lead frame and low logic-power dissipation
allow the dual in-line package to sink 122 mA through all outputs
continuously over the operating temperature range (1.0 V drop,
+85°C).
FEATURES
s To 150 mA Constant-Current Outputs
s Under-Voltage Lockout
s Low-Power CMOS Logic and Latches
s High Data Input Rate
s Similar to Toshiba TD62715FN
s High/Low Output Current Function
Digital “Dim” Control
Always order by complete part number, e.g., A6277EA .

1 Page





A6277ELW pdf, ピン配列
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
VDD
IN
VDD
IN
Dwg. EP-010-11
OUTPUT ENABLE (active low)
VDD
IN
Dwg. EP-010-12
LATCH ENABLE and HIGH/LOW
VDD
OUT
Dwg. EP-010-13
Dwg. EP-063-6
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial Latch
Latch Contents
Output
Data Enable
Enable
Output Input I1 I2 I3 ... IN-1 IN Input
Output Contents
I1 I2 I3 ... IN-1 IN
H H R1 R2 ... RN-2 RN-1 RN-1
L L R1 R2 ... RN-2 RN-1 RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H P1 P2 P3 ... PN-1 PN L
P1 P2 P3 ... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
3


3Pages


A6277ELW 電子部品, 半導体
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT1.
AB
DATA
50%
tp
50%
SERIAL
DATA OUT.2
LATCH
ENABLE
D
DATA
tp
50% DATA
E
50%
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
OUT N
OUTPUT
ENABLE
OUT N
t p HIGH = OUTPUT OFF
50% DATA
LOW = OUTPUT ON
Dwg. WP-029-3
HIGH = ALL OUTPUTS DISABLED (BLANKED)
50%
F
t en(BQ)
t dis(BQ)
tf
tr
90%
DATA
10%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
Max. Clock Transition Time, tr or tf .............................. 10 µs
Dwg. WP-030-1
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
115 Northeast Cutoff, Box 15036
6 Worcester, Massachusetts 01615-0036 (508) 853-5000

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