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PDF A6275EA Data sheet ( 特性 )

部品番号 A6275EA
部品説明 8-BIT SERIAL-INPUT/ CONSTANTCURRENT LATCHED LED DRIVER
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 

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A6275EA Datasheet, A6275EA PDF,ピン配置, 機能
6275
8-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
A6275ELW
GROUND 1
SERIAL
DATA IN 2
CLOCK 3 CK
LATCH 4
ENABLE
OUT 0 5
L
OUT 1 6
OUT2 7
OUT3 8
VDD
16
LOGIC
SUPPLY
IO
REGULATOR
15 REXT
SERIAL
14 DATA OUT
REGISTER
LATCHES
OE 13 OUTPUT
ENABLE
12 OUT7
11 OUT6
10 OUT5
9 OUT4
Dwg. PP-029-10
Note that the A6275EA (DIP) and the A6275ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD ...................... 7.0 V
Output Voltage Range,
VO ............................ -0.5 V to +17 V
Output Current, IO ........................ 90 mA
Ground Current, IGND ................. 750 mA
Input Voltage Range,
VI .................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
PD ..................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +85°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still suscep-
tible to damage if exposed to extremely high
static electrical charges.
The A6275EA and A6275ELW are specifically designed for LED-
display applications. Each BiCMOS device includes an 8-bit CMOS
shift register, accompanying data latches, and eight npn constant-
current sink drivers. Except for package style and allowable package
power dissipation, the two devices are identical.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is deter-
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. Similar 150 mA output devices are
available as the A6277EA and A6277ELW; similar 16-bit devices
are available as the A6276EA and A6276ELW.
Two package styles are provided for through-hole DIP (suffix A) or
surface-mount SOIC (suffix LW). Under normal applications, copper
lead frames and low logic-power dissipation allow these devices to
sink maximum rated current through all outputs continuously over the
operating temperature range (90 mA, 0.9 V drop, +85°C). Both
devices are also available for operation over the standard temperature
range of -20°C to +85°C. To order, change the suffix letter ‘E’ to ‘S’.
FEATURES
s To 90 mA Constant-Current Outputs
s Under-Voltage Lockout
s Low-Power CMOS Logic and Latches
s High Data Input Rate
s Pin-Compatible with TB62705CP
Always order by complete part number, e.g., A6275EA .

1 Page





A6275EA pdf, ピン配列
6275
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
VDD
IN
VDD
IN
Dwg. EP-010-11
OUTPUT ENABLE (active low)
VDD
IN
Dwg. EP-010-12
LATCH ENABLE
VDD
OUT
Dwg. EP-010-13
CLOCK and SERIAL DATA IN
Dwg. EP-063-6
SERIAL DATA OUT
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial Latch
Latch Contents
Output
Data Enable
Enable
Output Input I1 I2 I3 ... IN-1 IN Input
Output Contents
I1 I2 I3 ... IN-1 IN
H H R1 R2 ... RN-2 RN-1 RN-1
L L R1 R2 ... RN-2 RN-1 RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H P1 P2 P3 ... PN-1 PN L
P1 P2 P3 ... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
3


3Pages


A6275EA 電子部品, 半導体
6275
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
LATCH
ENABLE
OUTPUT
ENABLE
C
50%
AB
DATA
50%
tp
50%
D
E
50%
DATA
LOW = ALL OUTPUTS ENABLED
OUT N
t p HIGH = OUTPUT OFF
50% DATA
LOW = OUTPUT ON
Dwg. WP-029-1
OUTPUT
ENABLE
OUT N
HIGH = ALL OUTPUTS DISABLED (BLANKED)
50%
F
t en(BQ)
t dis(BQ)
tf
tr
90%
DATA
10%
Dwg. WP-030-1
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
Max. Clock Transition Time, tr or tf .............................. 10 µs
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

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