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A42U2604V-50 の電気的特性と機能

A42U2604V-50のメーカーはAMIC Technologyです、この部品の機能は「4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 A42U2604V-50
部品説明 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
メーカ AMIC Technology
ロゴ AMIC Technology ロゴ 




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A42U2604V-50 Datasheet, A42U2604V-50 PDF,ピン配置, 機能
A42U2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial issue
Modify symbol HE dimensions in TSOP 24L package information
Modify AC. and DC. data
Modify DC data and all parts guarantee self-refresh mode
Issue Date
June 13, 2001
July 10, 2001
December 12, 2001
June 10, 2002
Remark
Preliminary
PRELIMINARY (June, 2002, Version 0.3)
AMIC Technology, Inc.

1 Page





A42U2604V-50 pdf, ピン配列
Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
Functional Description
The A42U2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 4 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42U2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (tcp). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
A42U2604 Series
-50 -60 -80 Unit
50 60 80 ns
22 27 37 ns
13 15 20 ns
13 15 20 ns
84 100 132 ns
20 24 32 ns
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
PRELIMINARY (June, 2002, Version 0.3)
2
AMIC Technology, Inc.


3Pages


A42U2604V-50 電子部品, 半導体
A42U2604 Series
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . -0.5V to VCC+0.5V
Output Voltage (Vout) . . . . . . . . . . . . . -0.5V to VCC+0.5V
Power Supply Voltage (VCC) . . . . . . . -0.5V to VCC+0.5V
Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Symbol
Parameter
IIL Input Leakage
Current
IOL Output Leakage
Current
ICC1 Operating Power
Supply Current
ICC2 TTL Standby Power
Supply Current
ICC3 Average Power
Supply Current,
RAS Refresh Mode
ICC4 EDO Page Mode
Average Power
Supply Current
ICC5 CAS -before- RAS
Refresh Power
Supply Current
ICC6 CMOS Standby
Power Supply
Current
ICC7 Self Refresh Mode
Current
VOH
Output Voltage
VOL
-50 -60
Min. Max. Min. Max.
-5 +5 -5 +5
-5 +5 -5 +5
- 70 - 65
- 0.5 - 0.5
- 70 - 65
- 70 - 65
- 70 - 65
- 0.2 - 0.2
- 300 - 300
2.0 - 2.0 -
- 0.4 - 0.4
-80
Min. Max.
-5 +5
-5 +5
- 60
- 0.5
Unit
µA
µA
mA
mA
Test Conditions
0V Vin Vin + 0.2V
Pins not under
Test = 0V
DOUT disabled,
0V Vout + VCC
RAS ,UCAS ,LCAS
Address cycling; tRC = min.
RAS =UCAS =LCAS =VIH
Notes
1, 2
- 60 mA RAS cycling,
UCAS =LCAS = VIH,
tRC = min.
1
- 60 mA RAS = VIL,
1, 2
UCAS ,LCAS Address
cycling; tPC = min.
- 60 mA RAS , UCAS , LCAS
cycling; tRC = min.
1
- 0.2 mA RAS =UCAS =LCAS =
VCC - 0.2V
- 300 µA RAS = CAS VSS+0.2V
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
2.0 -
V IOUT = -2mA
- 0.4 V IOUT = 2mA
PRELIMINARY (June, 2002, Version 0.3)
5
AMIC Technology, Inc.

6 Page



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部品番号部品説明メーカ
A42U2604V-50

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

AMIC Technology
AMIC Technology
A42U2604V-50U

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

AMIC Technology
AMIC Technology


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