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A428316 の電気的特性と機能

A428316のメーカーはAMIC Technologyです、この部品の機能は「256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 A428316
部品説明 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
メーカ AMIC Technology
ロゴ AMIC Technology ロゴ 




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A428316 Datasheet, A428316 PDF,ピン配置, 機能
A428316 Series
Preliminary
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial issue
Modify AC data
Modify DC data and all parts guarantee self-refresh mode
Delete -30,-40 grade and add -25 grade
Issue Date
June 13, 2001
April 26, 2002
June 10, 2002
August 20, 2002
Remark
Preliminary
PRELIMINARY (August, 2002, Version 0.3)
AMIC Technology, Inc.

1 Page





A428316 pdf, ピン配列
A428316 Series
Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
-25 -35 Unit
25 35 ns
12 17 ns
8 10 ns
8 10 ns
44 62 ns
12 16 ns
Functional Description
The A428316 reads and writes data by multiplexing an 18-
bit address into a 9-bit row and 9-bit column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
The A428316 has two CAS inputs: LCAS controls I/O0-
I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using LCAS
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A428316 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the CAS precharge time (tcp).
Since data can be output after CAS goes high, the user is
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
once every 8ms through any RAS cycle (Read, Write) or
RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
PRELIMINARY (August, 2002, Version 0.3)
2
AMIC Technology, Inc.


3Pages


A428316 電子部品, 半導体
A428316 Series
Absolute Maximum Ratings*
*Comments
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . . . -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Symbol
Parameter
IIL Input Leakage Current
IOL Output Leakage Current
ICC1 Operating Power Supply
Current
ICC2 TTL Supply Current Supply
Current
-25
Min. Max.
-5 +5
-5 +5
- 115
- 2.5
-35
Min. Max.
-5 +5
-5 +5
- 105
- 2.5
Unit Test Conditions
µA 0V Vin VCC
Pins not under
Test = 0V
µA DOUT disabled,
0V Vout VCC
mA RAS ,UCAS ,LCAS and
Address cycling;
tRC = min.
mA RAS =UCAS =LCAS = VIH
Notes
1, 2
ICC3 Average Power Supply
Current, RAS Refresh
Mode
-
115
-
105 mA RAS and Address cycling,
1
UCAS =LCAS = VIH,
tRC = min.
ICC4 EDO Page Mode Average
Power Supply Current
- 115 - 105 mA RAS and address = VIL,
UCAS ,LCAS and
Address cycling;
tPC = min.
1, 2
ICC5 CAS -before- RAS Refresh
-
115
-
105 mA RAS and UCAS or
Power Supply Current
LCAS cycling;
tRC = min.
1
ICC6 CMOS Standby Power
Supply Current
- 1.0 - 1.0 mA RAS =UCAS =LCAS =
VCC - 0.2V
ICC7 Self Refresh Mode Current
-
1.0
-
1.0 mA RAS = CAS VSS+0.2V
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
VOH
Output Voltage
VOL
2.4 - 2.4 - V IOUT = -5.0mA
- 0.4 - 0.4 V IOUT = 4.2mA
PRELIMINARY (August, 2002, Version 0.3)
5
AMIC Technology, Inc.

6 Page



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256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

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