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AD10265 の電気的特性と機能

AD10265のメーカーはAnalog Devicesです、この部品の機能は「65 MSPS A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD10265
部品説明 65 MSPS A/D Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD10265 Datasheet, AD10265 PDF,ピン配置, 機能
aDual Channel, 12-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
AD10265
FEATURES
Dual, 65 MSPS Minimum Sample Rate
Channel-Channel Matching, ؎0.1% Gain Error
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Selectable Bipolar Input Voltage Range
(؎0.5 V, ؎1.0 V, ؎2.0 V)
Gain Flatness up to Nyquist: < 0.5 dB
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.05 W Per Channel
Industrial and Military Grade
APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Anti-Jamming Receivers
Multichannel, Multimode Receivers
PRODUCT DESCRIPTION
The AD10265 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
includes two wide dynamic range AD6640 ADCs. Each AD6640
has an AD9631/AD9632 ac-coupled amplifier front end. The
AD6640s have on-chip track-and-hold circuitry, and utilize an
innovative multipass architecture, to achieve 12-bit, 65 MSPS
performance. The AD10265 uses innovative high-density
circuit design and laser-trimmed thin-film resistor networks to
achieve exceptional matching and performance while still main-
taining excellent isolation, and providing for significant board
area savings.
The AD10265 operates with ± 5.0 V for the analog signal
conditioning with a separate +3.3 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent Encode and Analog
inputs. The AD10265 also offers the user a choice of Analog
Input Signal ranges to further minimize additional external
signal conditioning, while still remaining general-purpose.
The AD10265 is packaged in a 68-lead ceramic gull wing pack-
age, footprint compatible with the earlier generation AD10242
(12-bit, 40 MSPS). Manufacturing is done on Analog Devices’
MIL-38534 Qualified Manufacturers Line (QML) and com-
ponents are available up to Class-T (–25°C to +125°C). The
AD6640 internal components are manufactured on Analog
Devices’ high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input amplitude options, user configurable.
3. Input signal conditioning included; both channels matched
for gain.
4. Fully tested/characterized performance for full channel.
5. Footprint compatible family; 68-lead LCCC.
AINA3
FUNCTIONAL BLOCK DIAGRAM
AINA2
AINA1
AINB3
AINB2
AINB1
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD9632
AD9631
AD9632
AD9631
9
TIMING
AIN AIN
AD6640
12
OUTPUT BUFFERING
AD10265
AIN AIN
AD6640
12
OUTPUT BUFFERING
7
TIMING
5
ENCODEB
ENCODEB
D11B (MSB)
D10B
D9B
D8B
D7B
ENCODEA ENCODEA D9A D10A D11A
(MSB)
D0B D1B D2B D3B D4B D5B D6B
(LSB)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

1 Page





AD10265 pdf, ピン配列
AD10265
Parameter
Temp
Test
Level
Mil
Subgroup
AD10265AZ
Min Typ Max
Unit
SPURIOUS-FREE DYNAMIC RANGE9
Analog Input @ 1.24 MHz
25°C
I
4
Full II 5, 6
@ 17 MHz
25°C
I
4
Full II 5, 6
@ 32 MHz
25°C
V
Full V
75 80
74 80
71 80
70 79
79
79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
TWO-TONE IMD REJECTION10
f1, f2 @ –7 dBFS
Full V 4, 5, 6 66 77
dBc
CHANNEL-TO-CHANNEL ISOLATION11 25°C
IV 12
80
dB
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(Encode = 20 MHz)
25°C
Full
IV 12
V
–1.0 ± 0.5 +1.5 LSB
± 1.25
LSB
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
CMOS
Full
I
1, 2, 3
2.8 DVCC – 0.2
V
Full I 1, 2, 3
0.2 0.5 V
Two’s Complement
POWER SUPPLY
AVCC Supply Voltage
I (AVCC) Current
AVEE Supply Voltage
I (AVEE) Current
DVCC Supply Voltage
I (DVCC) Current
ICC (Total) Supply Current
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Full
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
I 1, 2, 3
I 1, 2, 3
IV 12
+5.0
336
–5.0
66
+3.3
20
422
2.1
0.01
V
mA
V
mA
V
mA
520 mA
2.4 W
0.02 % FSR/% VS
NOTES
1Gain tests are performed on AIN1 over specified input voltage range.
2Input capacitance specifications show only ceramic package capacitance.
3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
5ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD10265” for details.
6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 17.0 MHz
± 100 kHz, f2 = 18.0 MHz ± 100 kHz.
11Channel-to-channel isolation tested with A channel/50 ohm terminated <AIN2 grounded, and a full-scale signal applied to B channel (AIN1).
All specifications guaranteed within 100 ms of initial power-up, regardless of sequencing.
Specifications subject to change without notice.
REV. A
–3–


3Pages


AD10265 電子部品, 半導体
AD10265
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
–6– REV. A

6 Page



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部品番号部品説明メーカ
AD10265

65 MSPS A/D Converter

Analog Devices
Analog Devices


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