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AD5516 の電気的特性と機能

AD5516のメーカーはAnalog Devicesです、この部品の機能は「16-Channel/ 12-Bit Voltage-Output DAC with 14-Bit Increment Mode」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD5516
部品説明 16-Channel/ 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD5516 Datasheet, AD5516 PDF,ピン配置, 機能
a 16-Channel, 12-Bit Voltage-Output DAC
with 14-Bit Increment Mode
AD5516*
FEATURES
High Integration:
16-Channel DAC in 12 mm ؋ 12 mm LFBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic
Low Power, SPITM, QSPITM, MICROWIRETM, and DSP-
Compatible
3-Wire Serial Interface
Output Impedance 0.5
Output Voltage Range
؎2.5 V (AD5516-1)
؎5 V (AD5516-2)
؎10 V (AD5516-3)
Asynchronous Reset-Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40؇C to +85؇C
GENERAL DESCRIPTION
The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial interface.
DAC selection is accomplished via address bits A3–A0. 14-bit
resolution can be achieved by fine adjustment in Increment/
Decrement Mode (Mode 2). The serial interface operates at
clock rates up to 20 MHz and is compatible with standard SPI,
MICROWIRE, and DSP interface standards. The output volt-
age range is fixed at ± 2.5 V (AD5516-1), ± 5 V (AD5516-2),
and ± 10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via RFB0 to RFB15 pins.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –12 V, and VDD = +4.75 V to +12 V
and requires a stable 3 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. Sixteen 12-bit DACs in one package, guaranteed monotonic
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O
2. Available in a 74-lead LFBGA package with a body size of
12 mm ؋ 12 mm
FUNCTIONAL BLOCK DIAGRAM
RESET
BUSY
DACGND
AGND
DGND
DCEN
DVCC
AVCC
AD5516
ANALOG
CALIBRATION
LOOP
MODE1
INTERFACE
CONTROL
LOGIC
REF_IN
VBIAS
VDD
VSS
RO F F S
RFB
DAC
RO F F S
RFB
DAC
RO F F S
RFB
DAC
RO F F S
RFB
MODE2
7-BIT BUS
DAC
POWER-DOWN
LOGIC
RFB0
VOUT0
RFB1
VOUT1
RFB14
VOUT14
RFB15
VOUT15
SCLK DIN DOUT SYNC
*Protected by U.S. Patent No. 5,969,657; other patents pending
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PD
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

1 Page





AD5516 pdf, ピン配列
AD5516
AC CHARACTERISTICS (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND
= DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Parameter1, 2
Output Voltage Settling Time (Mode 1)4
Output Voltage Settling Time (Mode 2)4
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk AD5516-1
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
A Version3
32
2.5
0.85
1
5
10
1
150
Unit
s max
s max
V/s typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Conditions/Comments
100 pF, 5 kLoad Full-Scale Change
100 pF, 5 kLoad, 1 Code Increment
1 LSB Change around Major Carry
AD5516-1
NOTES
1See Terminology section.
2Guaranteed by design and characterization; not production tested.
3A version: Industrial temperature range –40°C to +85°C.
4 Timed from the end of a write sequence.
Specifications subject to change without notice.
TIMING CHARACTERISTICS (VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
Limit at TMIN, TMAX
Parameter1, 2, 3 (A Version)
Unit
Conditions/Comments
fUPDATE1
fUPDATE2
fCLKIN
t1
t2
t3
t4
t5
t6
t7
t7MODE2
t8MODE1
t9MODE2
t10
t114
t12
32
750
20
20
20
15
5
5
0
10
400
10
200
10
20
20
kHz max
kHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
DAC Update Rate (Mode 1)
DAC Update Rate (Mode 2)
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
DIN Setup Time
DIN Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Standalone Mode)
Minimum SYNC High Time (Daisy-Chain Mode)
BUSY Rising Edge to SYNC Falling Edge
18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
SCLK Rising Edge to DOUT Valid (Daisy-Chain Mode)
RESET Pulsewidth
NOTES
1See Timing Diagrams in Figures 1 and 2.
2Guaranteed by design and characterization; not production tested.
3All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
4This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
–3–


3Pages


AD5516 電子部品, 半導体
AD5516
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F TOP VIEW
G
H
J
K
L
A
B
C
D
E
F
G
H
J
K
L
1 2 3 4 5 6 7 8 9 10 11
LFBGA Ball
Number Name
LFBGA
Number
A1 NC
B5
A2 NC
B6
A3
RESET
B7
A4
BUSY
B8
A5
DGND
B9
A6 DVCC B10
A7 DOUT B11
A8 DIN
C1
A9
SYNC
C2
A10 NC
C6
A11 NC
C10
B1 NC
C11
B2 NC
D1
B3 NC
D2
B4
DCEN
D10
NC = Not Internally Connected
74-LEAD LFBGA BALL CONFIGURATION
Ball
Name
LFBGA Ball
Number Name
LFBGA
Number
DGND
DGND
NC
NC
SCLK
NC
REF_IN
VOUT0
DACGND
NC
AVCC1
NC
RFB0
DACGND
AVCC2
D11
E1
E2
E10
E11
F1
F2
F10
F11
G1
G2
G10
G11
H1
H2
NC
VOUT1
NC
AGND1
PD
VOUT2
RFB1
AGND2
RFB14
RFB2
RFB15
VOUT14
RFB13
VOUT3
VOUT15
H10
H11
J1
J2
J6
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
Ball
Name
VOUT13
VOUT12
RFB3
VOUT14
NC
RFB12
RFB11
RFB4
VOUT5
RFB5
NC
VSS2
VSS1
VOUT10
VOUT9
LFBGA Ball
Number Name
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
RFB10
RFB9
VOUT11
NC
VOUT6
RFB6
VOUT7
NC
VDD2
VDD1
RFB7
VOUT8
RFB8
NC
Mnemonic
AGND (1–2)
AVCC (1–2)
VDD (1–2)
VSS (1–2)
DGND
DVCC
DACGND
REF_IN
VOUT (0–15)
RFB (0–15)
SYNC
SCLK
DIN
PIN FUNCTION DESCRIPTIONS
Function
Analog GND pins
Analog supply pins. Voltage range from +4.75 V to +5.25 V.
VDD supply pins. Voltage range from +4.75 V to +15.75 V.
VSS supply pins. Voltage range from –4.75 V to –15.75 V.
Digital GND pins
Digital supply pin. Voltage range from 2.7 V to 5.25 V.
Reference GND supply for all 16 DACs.
Reference input voltage for all 16 DACs. The recommended value of REF_IN is 3 V.
Analog output voltages from the 16 DAC channels.
Feedback resistors. For nominal output voltage range connect each RFB to its corresponding VOUT.
Active low input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial clock input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 20 MHz.
Serial data input. Data must be valid on the falling edge of SCLK.
–6– REV. 0

6 Page



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共有リンク

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