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AD5316 の電気的特性と機能

AD5316のメーカーはAnalog Devicesです、この部品の機能は「8-/10-/12-Bit DACs」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD5316
部品説明 8-/10-/12-Bit DACs
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD5316 Datasheet, AD5316 PDF,ピン配置, 機能
2.5 V to 5.5 V, 400 μA, 2-Wire Interface,
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5306/AD5316/AD5326
FEATURES
AD5306: 4 buffered, 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL; B version: ±0.625 LSB INL
AD5316: 4 buffered, 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL; B version: ±2.5 LSB INL
AD5326: 4 buffered, 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL; B version: ±10 LSB INL
Low power operation: 400 μA @ 3 V, 500 μA @ 5 V
2-wire (I2C®-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 90 nA @ 3 V, 300 nA @ 5 V (PD pin or bit)
Double-buffered input logic
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC pin)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFA VREFB
AD5306/AD5316/AD5326
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING BUFFER
DAC A
VOUTA
SCL
SDA
A1
A0
LDAC
INTERFACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
STRING BUFFER
DAC B
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING BUFFER
DAC C
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING BUFFER
DAC D
VOUTD
VREFD VREFC
POWER-DOWN
LOGIC
PD GND
Figure 1.
GENERAL DESCRIPTION
The AD5306/AD5316/AD53261 are quad 8-/10-/12-bit buffered
voltage output DACs in 16-lead TSSOP packages that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus-compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
Each DAC has a separate reference input that can be configured
as buffered or unbuffered. The outputs of all DACs can be
updated simultaneously using the asynchronous LDAC input.
The parts incorporate a power-on reset circuit that ensures the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The software clear function
clears all DACs to 0 V. The parts contain a power-down feature
that reduces the current consumption of the device to
300 nA @ 5 V (90 nA @ 3 V).
All three parts have the same pinout, which allows users to select
the amount of resolution appropriate for their application without
redesigning their circuit board.
1 Protected by U.S. Patent Numbers 5,969,657 and 5,684,481.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

1 Page





AD5316 pdf, ピン配列
AD5306/AD5316/AD5326
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Version1
B Version1
Parameter 2
Min Typ
Max Min Typ
Max Unit
Conditions/Comments
DC PERFORMANCE3, 4
AD5306
Resolution
8
8 Bits
Relative Accuracy
±0.15
±1
±0.15
±0.625 LSB
Differential Nonlinearity
±0.02
±0.25
±0.02
±0.25
LSB
Guaranteed monotonic by
design over all codes.
AD5316
Resolution
10
10 Bits
Relative Accuracy
±0.5 ±4
±0.5 ±2.5 LSB
Differential Nonlinearity
±0.05
±0.5
±0.05
±0.5 LSB
Guaranteed monotonic by
design over all codes.
AD5326
Resolution
12
12 Bits
Relative Accuracy
±2 ±16
±2 ±10 LSB
Differential Nonlinearity
±0.2 ±1
±0.2 ±1 LSB
Guaranteed monotonic by
design over all codes.
Offset Error
±5 ±60
±5 ±60 mV
VDD = 4.5 V, gain = 2;
see Figure 4 and Figure 5.
Gain Error
Lower Deadband5
±0.3 ±1.25
10 60
±0.3
±1.25
% of FSR
VDD = 4.5 V, gain = 2;
see Figure 4 and Figure 5.
10 60 mV
See Figure 4; lower
deadband exists only if
offset error is negative.
Upper Deadband5
Offset Error Drift6
10 60
−12
10 60 mV
See Figure 5; upper
deadband exists only if
VREF = VDD and offset plus
gain error is positive.
–12 ppm of FSR/°C
Gain Error Drift6
–5
–5 ppm of FSR/°C
DC Power Supply
Rejection Ratio6
–60
–60 dB ΔVDD = ±10%.
DC Crosstalk6
200
200 μV RL = 2 kΩ to GND or VDD.
DAC REFERENCE INPUTS6
VREF Input Range
VREF Input Impedance
1
0.25
>10
VDD 1
VDD 0.25
>10
VDD V
VDD V
Buffered reference mode.
Unbuffered reference mode.
Buffered reference mode
and power-down mode.
Reference Feedthrough
148 180
74 90
−90
148 180
74 90
−90
kΩ Unbuffered reference mode;
0 V to VREF output range.
kΩ Unbuffered reference mode;
0 V to 2 VREF output range.
dB Frequency = 10 kHz.
Channel-to-Channel Isolation
−75
−75 dB Frequency = 10 kHz.
OUTPUT CHARACTERISTICS6
Minimum Output Voltage7
0.001
0.001
V This is a measure of the
minimum and maximum
drive capability of the
output amplifier.
Maximum Output Voltage7
VDD − 0.001
VDD − 0.001
V
DC Output Impedance
0.5
0.5 Ω
Rev. F | Page 3 of 24


3Pages


AD5316 電子部品, 半導体
AD5306/AD5316/AD5326
TIMING CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter2
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
t12
t13
CB4
A, B Versions
Limit at TMIN, TMAX
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1CB4
20
400
400
Unit
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
pF max
Conditions/Comments
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
LDAC pulse width
SCL rising edge to LDAC rising edge
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
SCL
START
CONDITION
t9
t3
t4
t10
t6
t11
t2
t5
REPEATED START
CONDITION
t4
t1
t7
LDAC1
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8 t12
Rev. F | Page 6 of 24

6 Page



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