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AD5203 の電気的特性と機能

AD5203のメーカーはAnalog Devicesです、この部品の機能は「4-Channel/ 64-Position Digital Potentiometer」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD5203
部品説明 4-Channel/ 64-Position Digital Potentiometer
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD5203 Datasheet, AD5203 PDF,ピン配置, 機能
a
4-Channel, 64-Position
Digital Potentiometer
AD5203
FEATURES
64 Position
Replaces Four Potentiometers
10 k, 100 k
Power Shutdown—Less than 5 A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 k, or 100 khas a ± 1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
DGND
SDI
CLK
CS
AD5203
1
DAC 2
SELECT
3
4
A1, A0
2
8-BIT
SERIAL
LATCH
6
D
CK Q RS
6-BIT
LATCH
6
CK RS
DAC 1
SHDN
A1
W1
B1
AGND1
6-BIT
LATCH
6
CK RS
DAC 2
SHDN
A2
W2
B2
AGND2
6-BIT
LATCH
6
CK RS
DAC 3
SHDN
A3
W3
B3
AGND3
6-BIT
LATCH
6
CK RS
DAC 4
SHDN
A4
W4
B4
AGND4
SDO
RS
SHDN
The reset RS pin forces the wiper to the midscale position by
loading 20H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

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AD5203 pdf, ピン配列
AD5203
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage
inputs result in minimum power dissipation.
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10All dynamic characteristics use V DD = +5 V.
11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.
13Propagation delay depends on value of V DD, RL and CL. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
IAB, IAW, IBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance θJA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I. Serial-Data Word Format
ADDR
DATA
B7 B6 B5 B4 B3 B2 B1
A1 A0 D5 D4 D3 D2 D1
MSB LSB MSB
27 26 25
B0
D0
LSB
20
1
SDI
0
1
CLK
0
1
CS
0
VOUT VDD
0V
A1 A0 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 1a. Timing Diagram
SDI 1
(DATA IN) 0
Ax OR Dx
SDO
(DATA OUT)
CLK
CS
1
A'x OR D'x
0
tPD MIN
t CH
1
0
t CSS
1
0
VDD
VOUT
0V
Ax OR Dx
tDS tDH
A'x OR D'x
tPD MAX
t CS1
tCL tCSH
t CSW
tS
؎ 1 LSB ERROR BAND
؎1 LSB
Figure 1b. Detail Timing Diagram
1
RS
0
VDD
VOUT
0V
t RS
tS
؎1 LSB ERROR BAND
؎1 LSB
Figure 1c. Reset Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–


3Pages


AD5203 電子部品, 半導体
AD5203–Typical Performance Characteristics
RW
(20mV/DIV)
CS
(5V/DIV)
TIME 500ns/DIV
Figure 11. One Position Step Change
at Half-Scale (Code 1FH to 20H)
0
CODE = 3FH
–10 20H
10H
–20 08H
04H
–30 02H
01H
–40
TA = +25؇C
SEE TEST CIRCUIT FIGURE 32
–50
10 100 1k 10k 100k
FREQUENCY – Hz
1M
10M
Figure 12. Gain vs. Frequency for
R = 10 k
0.75
0.5
0.25
0
–0.25
VDD = +5V
CODE = 3FH
SS = 77 UNITS
AVG +2
AVG
AVG –2
–0.5
–0.75
0
100 200 300 400 500
HOURS OF OPERATION @ 150؇C
␣ ␣ ␣ ␣ Figure 13. Long-Term Drift
Accelerated by Burn-In
600
OUTPUT
CS
TIME 5s/DIV
Figure 14. Large Signal Settling Time
10
FILTER = 22kHz
VDD = +5V
1
TA = +25؇C
RAB = 10k
0.1
SEE TEST CIRCUIT FIGURE 31
0.01
SEE TEST CIRCUIT FIGURE 30
0.001
10
100 1k 10k
FREQUENCY – Hz
100k
Figure 15.␣ Total Harmonic Distortion
Plus Noise vs. Frequency
0
CODE = 3FH
–10 20H
10H
–20 08H
04H
–30
02H
–40 VDD = +5V
TA = +25؇C
5dB/DIV
01H
–50
10 100 1k 10k 100k
FREQUENCY – Hz
1M
Figure 17. 100 kGain vs. Frequency
vs. Code
0
–0.1
RAB = 10k
–0.2
–0.3
–0.4
RAB = 100k
–0.5
–0.6
–0.7 VDD = +5V
–0.8
CODE = 3FH
TA = +25؇C
–0.9 SEE TEST CIRCUIT FIGURE 32
–1.0
10
100 1k 10k 100k
FREQUENCY – Hz
1M
Figure 18. Normalized Gain Flat-
ness vs. Frequency
VOUT
(20mV/DIV)
TIME 100ns/DIV
Figure 16. Digital Feedthrough vs.
Time
10
VDD = +5.0V
1
VDD = +3.0V
0.1
0.01
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT LOGIC VOLTAGE – Volts
Figure 19. Supply Current vs. Logic
Input Voltage
–6– REV. 0

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