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AD640 の電気的特性と機能

AD640のメーカーはAnalog Devicesです、この部品の機能は「DC-Coupled Demodulating 120 MHz Logarithmic Amplifier」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD640
部品説明 DC-Coupled Demodulating 120 MHz Logarithmic Amplifier
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD640 Datasheet, AD640 PDF,ピン配置, 機能
a
DC-Coupled Demodulating
120 MHz Logarithmic Amplifier
AD640*
FEATURES
Complete, Fully Calibrated Monolithic System
Five Stages, Each Having 10 dB Gain, 350 MHz BW
Direct Coupled Fully Differential Signal Path
Logarithmic Slope, Intercept and AC Response are
Stable Over Full Military Temperature Range
Dual Polarity Current Outputs Scaled 1 mA/Decade
Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.)
Low Power Operation (Typically 220 mW at ؎5 V)
Low Cost Plastic Packages Also Available
APPLICATIONS
Radar, Sonar, Ultrasonic and Audio Systems
Precision Instrumentation from DC to 120 MHz
Power Measurement with Absolute Calibration
Wide Range High Accuracy Signal Compression
Alternative to Discrete and Hybrid IF Strips
Replaces Several Discrete Log Amp ICs
PRODUCT DESCRIPTION
The AD640 is a complete monolithic logarithmic amplifier. A single
AD640 provides up to 50 dB of dynamic range for frequencies
from dc to 120 MHz. Two AD640s in cascade can provide up to
95 dB of dynamic range at reduced bandwidth. The AD640 uses a
successive detection scheme to provide an output current propor-
tional to the logarithm of the input voltage. It is laser calibrated to
close tolerances and maintains high accuracy over the full military
temperature range using supply voltages from ±4.5 V to ± 7.5 V.
The AD640 comprises five cascaded dc-coupled amplifier/limiter
stages, each having a small signal voltage gain of 10 dB and a –3 dB
bandwidth of 350 MHz. Each stage has an associated full-wave
detector, whose output current depends on the absolute value of its
input voltage. The five outputs are summed to provide the video
output (when low-pass filtered) scaled at 1 mA per decade (50 µA
per dB). On chip resistors can be used to convert this output cur-
rent to a voltage with several convenient slope options. A balanced
signal output at +50 dB (referred to input) is provided to operate
AD640s in cascade.
The logarithmic response is absolutely calibrated to within ±1 dB
for dc or square wave inputs from ± 0.75 mV to ± 200 mV, with
an intercept (logarithmic offset) at 1 mV dc. An integral X10
attenuator provides an alternative input range of ± 7.5 mV to
± 2 V dc. Scaling is also guaranteed for sinusoidal inputs.
The AD640B is specified for the industrial temperature range of
–40°C to +85°C and the AD640T, available processed to MIL-
STD-883B, for the military range of –55°C to +125°C. Both are
available in 20-lead side-brazed ceramic DIPs or leadless chip
carriers (LCC). The AD640J is specified for the commercial
temperature range of 0°C to +70°C, and is available in both
20-lead plastic DIP (N) and PLCC (P) packages.
This device is now available to Standard Military Drawing
(DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTS
1. Absolute calibration of a wideband logarithmic amplifier is
unique. The AD640 is a high accuracy measurement device,
not simply a logarithmic building block.
2. Advanced design results in unprecedented stability over the
full military temperature range.
3. The fully differential signal path greatly reduces the risk of
instability due to inadequate power supply decoupling and
shared ground connections, a serious problem with com-
monly used unbalanced designs.
4. Differential interfaces also ensure that the appropriate ground
connection can be chosen for each signal port. They further
increase versatility and simplify applications. The signal input
impedance is ~500 kin shunt with ~2 pF.
5. The dc-coupled signal path eliminates the need for numerous
interstage coupling capacitors and simplifies logarithmic
conversion of subsonic signals.
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
COM 18
RG1 1kRG0 1kRG2
17 16 15
LOG OUT LOG COM
14 13
INTERCEPT POSITIONING BIAS
12 +VS
ATN OUT 19
SIG +IN 20
SIG –IN 1
ATN LO 2
ATN COM 3
ATN COM 4
27
30
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
270
5
ATN IN
6
BL1
*Protected under U.S. patent number 4,990,803.
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
10dB
10dB
10dB
10dB
AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER
GAIN BIAS REGULATOR
7 SLOPE BIAS REGULATOR
–VS
11 SIG +OUT
10 SIG –OUT
9 BL2
8 ITC
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 Page





AD640 pdf, ピン配列
AD640
AC SPECIFICATIONS (VS = ؎5 V, TA = +25؇C, unless otherwise noted)
Model
Parameter
Conditions
AD640J
Min Typ Max
AD640B
Min Typ Max
AD640T
Min Typ Max
Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance
Noise Spectral Density
Tangential Sensitivity
Either Pin to COM
1 kHz to 10 MHz
BW = 100 MHz
2
2
–72
2
2
–72
2 pF
2 nV/Hz
–72 dBm
3 dB BANDWIDTH
Each Stage
All Five Stages
LOGARITHMIC OUTPUTS5
Slope Current, IY
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
Intercept, Dual AD640s10, 11
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
Pins 1 & 20 to 10 & 11
350
145
350
145
350 MHz
145 MHz
0.96 1.0 1.04 0.98 1.0
1.02
0.88 0.94 1.00 0.91 0.94 0.97
0.82 0.90 0.98 0.86 0.90 0.94
0.88 0.88
0.85 0.85
–90.6
–88.6
–87.6
–86.3
–83.9
–80.3
–86.6
–89.6
–88.6
–87.6
–86.3
–83.9
–80.3
–87.6
0.98
0.91
0.86
–89.6
1.0 1.02
0.94 0.97
0.90 0.94
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
–87.6
mA
mA
mA
mA
mA
dBm
dBm
dBm
dBm
dBm
AC LINEARITY
–40 dBm to –2 dBm12
–35 dBm to –10 dBm12
–75 dBm to 0 dBm10
–70 dBm to –10 dBm10
–75 dBm to +15 dBm13
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 10 kHz
0.5 2.0
0.25 1.0
0.75 3.0
0.5 2.0
0.5 3.0
0.5 1.0
0.25 0.5
0.75 1.5
0.5 1.0
0.5 1.5
0.5 1.0
0.25 0.5
0.75 1.5
0.5 1.0
0.5 1.5
dB
dB
dB
dB
dB
PACKAGE OPTION
20-Lead Ceramic DIP Package (D)
20-Terminal Ceramic LCC (E)
20-Lead Plastic DIP Package (N)
20-Lead Plastic Leaded Chip Carrier (P)
AD640]N
AD640JP
AD640BD
AD640BE
AD640BP
AD640TD
AD640TE
NUMBER OF TRANSISTORS
155 155
155
NOTES
1Logarithms to base 10 are used throughout. The response is independent of the sign of V IN.
2Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C.
3Overall gain is trimmed using a ± 200 µV square wave at 2 kHz, corrected for the onset of compression.
4The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.
6The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG 10 (VX/1 V).
7The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8Operating in circuit of Figure 24 using ± 0.1% accurate values for RLA and RLB. Includes slope and nonlinearity errors. Input offset errors also included for
VIN >3 mV dc, and over the full input range in ac applications.
9Essentially independent of supply voltages.
10Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 = 223 mV rms.
11For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 = 223 mV rms.
13Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
20-Lead Ceramic DIP Package (D-20)
20-Terminal Ceramic LCC (E-20A)
20-Lead Plastic DIP Package (N-20)
20-Lead Plastic Leaded Chip Carrier (P-20A)
JC (؇C/W)
25
25
24
28
JA (؇C/W)
85
85
61
75
REV. C
–3–


3Pages


AD640 電子部品, 半導体
AD640–Typical AC Performance Characteristics
–2.5
–2.0
–1.5
30MHz
60MHz
90MHz
120MHz
–1.0
–0.5
0
0.5
–50
AD640 ؎VS = 5 VOLTS
TEMPERATURE = +25؇C
–40 –30 –20 –10
INPUT LEVEL – dBm
0
Figure 10. AC Response at 30 MHz, 60 MHz, 90 MHz and
120 MHz, vs. dBm Input (Sinusoidal Input)
1.0
0.95
0.90
0.85
0.80
DC
30 60 90 120
FREQUENCY – MHz
150
Figure 11. Slope Current, IY, vs. Input Frequency
–2.5
–2.0
+125؇C
+25؇C
–1.5
–1.0
–55؇C
–5
+125؇C
0
–55؇C
0.5
–50
–40
+125؇C +25؇C
–55؇C +1
+125؇C
+25؇C
AD640
FREQUENCY = 60MHz
–55؇C
0
–1
–2
–30 –20
INPUT LEVEL – dBm
–10
0
Figure 13. Logarithmic Response and Linearity at 60 MHz,
TA for TA = –55 ؇C, +25 ؇C, +125 ؇C
90
89
88
87
86
85
84
83
82
81
80
0
10 20 30 40 50 60 70 80 90 100 110 120
INPUT FREQUENCY – MHz
Figure 14. Intercept Level (dBm) vs. Frequency
(Cascaded AD640s – Sinusoidal Input)
5µs
100
90
5µs
Figure 12. Baseband Pulse Response of Single AD640,
Inputs of 1 mV, 10 mV and 100 mV
10
0%
20mV
20mV
Figure 15. Baseband Pulse Response of Cascaded
AD640s, Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
–6– REV. C

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