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AD9712B の電気的特性と機能

AD9712BのメーカーはAnalog Devicesです、この部品の機能は「12-Bit/ 100 MSPS D/A Converters」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9712B
部品説明 12-Bit/ 100 MSPS D/A Converters
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9712B Datasheet, AD9712B PDF,ピン配置, 機能
a
12-Bit, 100 MSPS
D/A Converters
FEATURES
100 MSPS Update Rate
ECL/TTL Compatibility
SFDR @ 1 MHz: 70 dBc
Low Glitch Impulse: 28 pV-s
Fast Settling: 27 ns
Low Power: 725 mW
1/2 LSB DNL (B Grade)
40 MHz Multiplying Bandwidth
APPLICATIONS
ATE
Signal Reconstruction
Arbitrary Waveform Generators
Digital Synthesizers
Signal Generators
GENERAL DESCRIPTION
The AD9712B and AD9713B D/A converters are replacements
for the AD9712 and AD9713 units which offer improved ac and
dc performance. Like their predecessors, they are 12-bit, high
speed digital-to-analog converters fabricated in an advanced
oxide isolated bipolar process. The AD9712B is an ECL-
compatible device featuring update rates of 100 MSPS mini-
mum; the TTL-compatible AD9713B will update at 80 MSPS
minimum.
AD9712B/AD9713B
FUNCTIONAL BLOCK DIAGRAM
LATCH 26
ENABLE
28
DIGITAL
INPUTS
D1
THRU
D12
1
AD9712B/AD9713B
(MSB)
DECODERS
AND
DRIVERS
SWITCH
NETWORK
11 (LSB)
R SET 24
INTERNAL
VOLTAGE
REFERENCE
+
CONTROL
AMP
20
REFERENCE
OUT
19
CONTROL
AMP IN
14 I OUT
16 I OUT
17 REFERENCE
IN
18 CONTROL
AMP OUT
Designed for direct digital synthesis, waveform reconstruction,
and high resolution imaging applications, both devices feature
low glitch impulse of 28 pV-s and fast settling times of 27 ns.
Both units are characterized for dynamic performance and have
excellent harmonic suppression.
The AD9712B and AD9713B are available in 28-pin plastic
DIPs and PLCCs, with an operating temperature range of
–25°C to +85°C. Both are also available for extended tempera-
ture ranges of –55°C to +125°C in cerdips and 28-pin LCC
packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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AD9712B pdf, ピン配列
AD9712B/AD9713B
Parameter (Conditions)
Temp
Test
Level Min
AD9712B
All Grades
Typ
Max
AD9713B
All Grades
Min Typ
Max
Units
POWER SUPPLY13
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V)14
Nominal Power Dissipation
Power Supply Rejection Radio (PSRR)15
+25°C
Full
+25°C
Full
+25°C
+25°C
I
VI
I
VI
V
I
140 178
183
728
30 100
6 12
14
145 184
188
784
30 100
mA
mA
mA
mA
mW
µA/V
NOTES
1Measured as error in ratio of full-scale current to current through R SET (160 µA nominal); ratio is nominally 128.
2Full-scale variations among devices are higher when driving REFERENCE INPUT directly.
3Frequency at which the gain is flat ± 0.5 dB; RL = 50 ; 50% modulation at midscale.
4Based on IFS = 128 (VREF/RSET) when using internal amplifier.
5Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy.
6Measured as voltage settling at midscale transition to ± 0.024%, RL = 50 .
7Measured as the time between the 50% point of the falling edge of LATCH ENABLE and the point where the output signal has left a 1 LSB error band
around its previous value.
8Peak glitch impulse is measured as the largest area under a single positive or negative transient.
9Measured with RL = 50 and DAC operating in latched mode.
10Data must remain stable for specified time prior to falling edge of LATCH ENABLE signal.
11Data must remain stable for specified time after rising edge of LATCH ENABLE signal.
12SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is
centered at the fundamental frequency and covers the indicated span.
13Supply voltages should remain stable within ± 5% for normal operation.
14108 mA typ on Digital –VS, 37 mA typ on Analog –VS.
15Measured at ± 5% of +VS (AD9713B only) and –VS (AD9712B or AD9713B) using external reference.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Positive Supply Voltage (+VS) (AD9713B Only) . . . . . . . +6 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . –7 V
Analog-to-Digital Ground Voltage Differential . . . . . . . . 0.5 V
Digital Input Voltages (D1–D12, LATCH ENABLE)
AD9712B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS
AD9713B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . . 500 µA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . . . ± 2.5 mA
Reference Input Voltage Range (VREF) . . . . . . . . . . . 0 V to –VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . –25°C to +85°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . –55°C to +125°C
Maximum Junction Temperature2
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . . . . . . . +150°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . . . . . . . . +175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Model
AD9712BAN
AD9712BBN
AD9712BAP
AD9712BBP
AD9712BSQ/883B
AD9712BSE/883B
AD9712BTQ/883B
AD9712BTE/883B
AD9713BAN
AD9713BBN
AD9713BAP
AD9713BBP
AD9713BSQ/883B
AD9713BSE/883B
AD9713BTQ/883B
AD9713BTE/883B
ORDERING GUIDE
Temperature
Range
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Description
Package
Option
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Typical thermal impedances with parts soldered in place: 28-pin plastic DIP:
θJA = 37°C/W, θJC = 10°C/W; 28-pin PLCC: θJA = 44°C/W, θJC = 14°C/W;
Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air
flow.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% tested at +25°C. 100% production
tested at temperature extremes for extended tempera-
ture devices; sample tested at temperature extremes for
commercial/industrial devices.
REV. B
–3–


3Pages


AD9712B 電子部品, 半導体
AD9712B/AD9713B
Full-scale output current is determined by CONTROL AMP
IN and RSET according to the equation:
IOUT (FS) = (CONTROL AMP IN/RSET) × 128
The internal reference is nominally –1.18 V with a tolerance of
± 3.5% and typical drift over temperature of 50 ppm/°C. If
greater accuracy or better temperature stability is required, an
external reference can be utilized. The AD589 reference shown
in Figure 1 features ± 10 ppm/°C drift over temperatures from
0°C to +70°C.
AD589
AD9712B
+ AD9713B
R1
~–11k
19 CONTROL
AMP IN
–VS
Figure 1. Use of AD589 as External Reference
Two modes of multiplying operation are possible with the
AD9712B/AD9713B. Signals with small signal bandwidths up
to 300 kHz and input swings of 100 mV, or dc signals from
–0.6 V to –1.2 V can be applied to the CONTROL AMP input
as shown in Figure 2. Because the control amplifier is internally
compensated, the 0.1 µF capacitor at Pin 17 can be reduced to
0.01 µF to maximize the multiplying bandwidth. However, it
should be noted that settling time for changes to the digital in-
puts will be degraded.
RSET
24 RSET
–0.6V TO –1.2V
300 kHz MAX
19 CONTROL
AMP IN
R T AD9712B
AD9713B
18 CONTROL
AMP OUT
18
17 REFERENCE
IN
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this
mode of operation must have a signal swing in the range of
–3.75 V to –4.25 V. This can be implemented by capacitively
coupling into REFERENCE IN a signal with a dc bias of –3.75 V
to –4.25 V, as shown in Figure 3; or by driving REFERENCE
IN with a low impedance op amp whose signal swing is limited
to the stated range.
Outputs
As indicated earlier, D1–D4 (four MSBs) are decoded and drive
15 discrete current sinks. D5 and D6 are binarily weighted; and
D7–D12 are applied to the R-2R network. This segmented archi-
tecture reduces frequency domain errors due to glitch impulse.
REFERENCE
IN
17
~–4V
AD9712B
AD9713B
–VS –VS
Figure 3. Wideband Multiplying Circuit
The Switch Network provides complementary current outputs
IOUT and IOUT. These current outputs are based on statistical
current source matching which provides 12-bit linearity without
trim. Current is steered to either IOUT or IOUT in proportion to
the digital input code. The sum of the two currents is always
equal to the full-scale output current minus one LSB.
The current output can be converted to a voltage by resistive
loading as shown in Figure 4. Both IOUT and IOUT should be
loaded equally for best overall performance. The voltage which
is developed is the product of the output current and the value
of the load resistor.
Figure 2. Low Frequency Multiplying Circuit
–6– REV. B

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部品番号部品説明メーカ
AD9712

100MSPS D/A CONVERTERS

Analog Devices
Analog Devices
AD9712B

12-Bit/ 100 MSPS D/A Converters

Analog Devices
Analog Devices


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