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PDF AD8401 Data sheet ( Hoja de datos )
| Número de pieza | AD8401 | |
| Descripción | 8-Bit/ 4-Channel Data Acquisition System | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
2 s ADC with T/H
4-Channel MUX
AD899 Compatible
+5 Volt Operation
On-Chip Reference
4 s Voltage Output DAC
Fast Bus Access Time—75 ns
APPLICATIONS
Servo Controls
Digitally Controlled Calibration
Process Control Equipment
8-Bit, 4-Channel Data
Acquisition System
AD8401
FUNCTIONAL BLOCK DIAGRAM
A0 A1 VDD (+5.0V)
VI NA
VINB
VI NC
VI ND
RS
INT
BUSY
ST
M
U T/H
X
8-BIT ADC
8-BIT
DAC
1.25 REF
VOUT
CONTROL LOGIC
DAC REG
ADC REG
AD8401
DGND RD CLK CS WR DATA I/O
(8 BITS)
AGDAC AGADC
GENERAL DESCRIPTION
The AD8401 is a complete data acquisition and control system
containing ADC, DAC, 4-channel MUX, and internal voltage
reference. Built using CBCMOS, this monolithic circuit offers
the user a complete system with very high package density and
reliability.
The converter is a successive approximation ADC with T/H,
and is capable of operating with conversion times as short as
2 µs. Analog input bandwidth is 200 kHz, and DAC output volt-
age settling time is less than 4 µs, making the AD8401 capable
of controlling servo loops with speed and precision.
The 8-bit data interface provides both read and write operation
for parallel bus interfaces to microcontrollers and DSP proces-
sors. An external 5 MHz clock sets the 2 µs conversion rate.
Slower clocks reduce the conversion time and the internal power
dissipation. The standard control lines: Reset, Busy, Interrupt,
Read and Write complete the handshaking signals for micro-
processor communication. A start trigger ST input allows pre-
cise sampling intervals in synchronous sampling applications.
The input multiplexer addressing is designed for direct interface
to the AD899 hard-disk drive, read-channel device with no extra
hardware or special software. Analog input range levels are like-
wise compatible with the AD899.
The AD8401 is designed to operate from a single +5 volt sup-
ply, which will give an ADC input range of 0 V to 3.0 V, and
DAC output range of 0 V to 2.5 V.
The AD8401 is offered in the SOIC-28 surface mount package,
and is guaranteed to operate over the extended industrial tem-
perature range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD8401
Pin#
1
2
3
4
5
6
7–12, 14, 15
13
16
17
18
19
20
21
22
23
27–24
28
REV. 0
PIN CONFIGURATION
DICE CHARACTERISTICS
VDD 1
AGDAC 2
VOUT 3
NC 4
A1 5
RS 6
DB7 7
DB6 8
DB5 9
28 A0
27 VINA
26 VINB
25 VINC
24 VIND
23 AGADC
AD8401AR
Top View
(Not to Scale)
22 CLK
21 INT
20 BUSY
DB4 10
19 ST
DB3 11
18 RD
DB2 12
17 CS
DGND 13
DB1 14
16 WR
15 DB0
NC = NO CONNECT
32
1
28 27
26
25
24
23
5
6
7
8
9
10
PIN DESCRIPTIONS
22
21
20
19
18
11 12 13 14 15 16 17
Die Size 91 X 121 mil = 11,011 sq mil
Name
VDD
AGDAC
VOUT
NC
A1
RESET (RS)
DB7 to DB0
DGND
WR
CS
RD
ST
BUSY
INT
CLK
AGADC
VINA, B, C, D
A0
Description
Positive Supply. Nominal value +5 volts. This pad requires 2 bonds for die assembly.
The substrate is common with VDD.
Analog Ground for the DAC. There is a separate analog ground for the ADC.
Voltage Output from the DAC.
No Connect.
Address Input that controls multiplexer. See Table I for address decode.
Active Low Digital Input that clears the DAC register to zero, setting the DAC to mini-
mum scale. It also asynchronously clears the INT line of the ADC.
Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and
the DAC, and DB0 (15) is the Least Significant Bit (LSB).
Digital Ground.
Rising Edge Triggered Write Input. Used to load data into the DAC register.
Chip Select. Active Low Input
Active Low Read Input. When this input is active, ADC data can be read from the
part. RD going low starts the ADC conversion.
Falling Edge Triggered Start Input. Used for applications requiring precise sample tim-
ing. The falling edge of ST starts the conversion and sets the BUSY low. The ST is not
gated by CS.
ADC Active Low, Status Output. When the ADC is performing a conversion, the
BUSY output is low.
Active Low Output. The Interrupt output notifies the system that the ADC has com-
pleted its conversion. INT goes high on the rising edge of CS or RD. It will also be
forced high when RESET is asserted.
External Clock Input Pin. Accepts a TTL or 5 V CMOS input logic levels.
Analog ADC Ground
Four Analog Inputs
Address input that controls multiplexer. See Table I for address decode.
–5–
5 Page 
AD8401
APPLICATIONS INFORMATION
The software programming needs to format data as defined by
the transfer equations and Code Tables that follow.
DAC Transfer Equation
V OUT
=
2.500
×
D
256
=
2.500
×
255
256
for
a
2.50
V
full
scale
where D is the decimal value 0 through 255 of the 8-bit data
word.
Table III. DAC Unipolar Code
DAC Register Contents
Decimal Binary
255 1111 1111
129 1000 0001
128 1000 0000
127 0111 1111
1 0000 0001
0 0000 0000
Nominal
Analog
General Transfer
Equation
Output VOUT
2.500
×
255
256
2.490 V
2.500
×
129
256
1.260 V
2.500
×
128
256
1.250 V
2.500
×
127
256
1.240 V
2.500
×
1
256
0.010 V
2.500
×
0
256
0.000 V
The nominal output voltages listed in the Code Table are sub-
ject to the static performance specifications. The INL, Zero-
Scale and Full-Scale errors describe the total specified variation
that will be encountered from part to part. One LSB of error for
the 2.5 V FS range is 9.766 millivolts (= 2.50/256).
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to signal interaction between the DAC and
ADC. Therefore, to ensure correct operation of the ADC, the
DAC register should not be updated while the ADC is converting.
The AD8401 is configured for an input range of +3.0 volts Full
Scale. The nominal transfer characteristic for this range is plot-
ted in Figure 23. The output coding is natural binary with one
LSB equal to 11.72 millivolts. Note that the first code transition
between 0 LSB and 1 LSB occurs at 5.8 mV, one half of the
11.72 mV LSB step size. The last code transition occurs at Full
Scale minus 1.5 LSBs, which is a 2.982 V input.
The AD8401 is easily interfaced to most microprocessors by us-
ing either address bits or address decode to select the appropri-
ate multiplexer channel. Figure 24 shows how easily the AD8401
interfaces to the AD899. No additional hardware is required.
OUTPUT
CODE
11111111
11111110
11111101
FULL SCALE
TRANSITION
00000011
1LSB = FS
256
00000010
00000001
FS – 1LSB
00000000
123
VIN INPUT VOLTAGE – LSBs
FS
Figure 23. ADC 0 V to +3 V Input Transfer Characteristic
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD8401.PDF ] | |
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