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ADV7172 の電気的特性と機能

ADV7172のメーカーはAnalog Devicesです、この部品の機能は「Digital PAL/NTSC Video Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7172
部品説明 Digital PAL/NTSC Video Encoder
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7172 Datasheet, ADV7172 PDF,ピン配置, 機能
a
Digital PAL/NTSC Video Encoder
with Six DACs (10 Bits), Color Control
and Enhanced Power Management
ADV7172/ADV7173
FEATURES
ITU-R1 BT601/656 YCrCb to PAL/NTSC Video Encoder
Six High Quality 10-Bit Video DACs
SSAF™ (Super Sub-Alias Filter)
Advanced Power Management Features
PC’98-Compliant (TV Detect with Polling and Auto
Shutdown to Save On Power Consumption)
Low Power DAC Mode
Individual DAC ON/OFF Control
Variable DAC Output Current (5 mA–36 mA)
Ultralow Sleep Mode Current
Hue, Brightness, Contrast and Saturation Controls
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
YUV Betacam, MII and SMPTE/EBU N10 Output Levels
Single 27 MHz Clock Required (؋2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV
EuroSCART RGB
Component YUV + CHROMA + LUMA + CVBS
EuroSCART Output RGB + CHROMA + LUMA + CVBS
Programmable Clamping Output Signal
Advanced Programmable Power-On Reset Sequencing
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Luma Sharpness Control
Programmable Luma Filters (Low-Pass [PAL/NTSC],
Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF)
Programmable Chroma Filters (Low-Pass [0.65 MHz,
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
NOTES
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.1 (ADV7172 Only)2
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C®-Compatible and Fast I2C)
Single Supply 5 V or 3.3 V Operation
Small 48-Lead LQFP Package
APPLICATIONS
High Performance DVD Playback Systems, Portable
Video Equipment including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)
GENERAL DESCRIPTION
The ADV7172/ADV7173 is an integrated Digital Video
Encoder that converts digital CCIR-601 4:2:2 8-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
There are six DACs available on the ADV7172/ADV7173. In
addition to the Composite output signal there is the facility to
output S-VHS Y/C Video, RGB Video and YUV Video.
The on-board SSAF (Super Sub-Alias Filter), with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness control
feature allows extra luminance boost on the frequency response.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power down or sleep modes. A PC’98-Compliant autodetect
feature has been added to allow the user to determine whether
or not the DACs are correctly terminated. If not, the ADV7172/
ADV7173 flags that they are not connected through the Status
bit and provides the option of automatically powering them
down, thereby reducing power consumption.
The ADV7172/ADV7173 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
1ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest
Macrovision version available.
SSAF is a trademark of Analog Devices, Inc.
I2C is a registered trademark of Philips Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

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ADV7172 pdf, ピン配列
SPECIFICATIONS
ADV7172/ADV7173
5 V SPECIFICATIONS (VAA = 5 V ؎ 5%1, VREF = 1.235 V, RSET1,2 = 600 unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
Parameter
Test Conditions1
Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity3
Differential Nonlinearity3
Guaranteed Monotonic
10 Bits
± 1.0 LSB
± 1.0 LSB
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
2V
0.8 V
± 1 µA
10 pF
2.4 V
0.4 V
10 µA
10 pF
ANALOG OUTPUTS
Output Current (DACs A, B, C)4
Output Current (DACs A, B, C)5
Output Current (DACs D, E, F)6
Output Current (DACs D, E, F)5
DAC-to-DAC Matching (DACs A, B, C)7
DAC-to-DAC Matching (DACs D, E, F)7
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE
Reference Range, VREF
POWER REQUIREMENTS
VAA
Normal Power Mode
IDAC (max)8, 9
IDAC (min)8, 9
ICCT10
Low Power Mode
IDAC (max)11
IDAC (min)11
ICCT10
Sleep Mode
IDAC12
ICCT13
Power Supply Rejection Ratio
RSET1 = 150 , RL = 37.5
RSET1 = 1041 , RL = 262.5
RSET2 = 600 , RL = 150
RSET2 = 1041 , RL = 262.5
IOUT = 0 mA
IVREFOUT = 20 µA
RSET1,2 = 600
RSET1,2 = 1041
RSET1 = 150
COMP = 0.1 µF
33
8.25
0
1.112
4.75
34.7
5
8.66
5
1
1
30
37
9.25
4.0
4.0
1.4
30
1.235 1.359
5.0 5.25
59 65
30
78 90
64
15
78 90
0.1
0.1
0.01 0.5
mA
mA
mA
mA
%
%
V
k
pF
V
V
mA
mA
mA
mA
mA
mA
µA
µA
%/%
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Characterized by design.
4Full drive into 75 doubly terminated load.
5Minimum drive current (used with buffered/scaled output load).
6Full drive into 150 load.
7Specification guaranteed by characterization.
8IDAC is the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC ) to drive DACs A, B, C, D, E, F. Turning off
individual DACs reduces IDAC correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA but DAC D, E, F must be turned off.
9All six DACs on (DAC A, B, C, D, E, F).
10ICCT (Circuit Current) is the continuous current required to drive the device.
11Only large DACs (DACs A, B, C) on per low power mode.
12Total DAC current in Sleep Mode.
13Total continuous current during Sleep Mode.
Specifications subject to change without notice.
REV. B
–3–


3Pages


ADV7172 電子部品, 半導体
ADV7172/ADV7173
5 V TIMING SPECIFICATIONS (VAA = 5 V ؎ 5%1, VREF = 1.235 V, RSET1 = 600 unless otherwise noted. All specifications TMIN
to TMAX2 unless otherwise noted.)
Parameter
Conditions
Min Typ Max Unit
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
After this period the 1st clock is generated
relevant for repeated Start Condition.
0
0.6
1.3
0.6
0.6
100
0.6
7
0
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
ns
CLOCK CONTROL AND
PIXEL PORT5, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
TELETEXT PORT3, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3
RESET Low Time
27 MHz
8 ns
8 ns
4.0 ns
5.0 ns
4 ns
3 ns
15 24 ns
10 ns
37 Clock Cycles
20 ns
2 ns
6 ns
3 ns
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
P7–P0
HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP
Clock Input:
CLOCK
7Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
–6– REV. B

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共有リンク

Link :


部品番号部品説明メーカ
ADV7170

Digital PAL/NTSC Video Encoder

Analog Devices
Analog Devices
ADV7171

Digital PAL/NTSC Video Encoder

Analog Devices
Analog Devices
ADV7172

Digital PAL/NTSC Video Encoder

Analog Devices
Analog Devices
ADV7173

Digital PAL/NTSC Video Encoder

Analog Devices
Analog Devices


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