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PDF ADS1271IPWR Data sheet ( Hoja de datos )
| Número de pieza | ADS1271IPWR | |
| Descripción | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
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ADS1271
SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004
24ĆBit, Wide Bandwidth
AnalogĆtoĆDigital Converter
FEATURES
D 105kSPS Data Rate
D AC Performance:
51kHz Bandwidth
109dB SNR (High-Resolution Mode)
−105dB THD
D DC Accuracy:
1.8µV/°C Offset Drift
2ppm/°C Gain Drift
D Selectable Operating Modes:
High-Speed: 105kSPS Data Rate
High-Resolution: 109dB SNR
Low-Power: 35mW Dissipation
D Power-Down Control
D Digital Filter:
Linear Phase Response
Passband Ripple: ±0.005dB
Stop Band Attenuation: 100dB
D Internal Offset Calibration On Command
D Selectable SPIt or Frame Sync Serial Interface
D Designed for Multichannel Systems:
Daisy-Chainable Serial Interface
Easy Synchronization
D Simple Pin-Driven Control
D Specified from −40°C to +105°C
D Analog Supply: 5V
D Digital Supply: 1.8V to 3.3V
APPLICATIONS
D Vibration/Modal Analysis
D Acoustics
D Dynamic Strain Gauges
D Pressure Sensors
D Test and Measurement
DESCRIPTION
The ADS1271 is a 24-bit, delta-sigma analog-to-digital
converter (ADC) with a data rate up to 105kSPS. It offers
a unique combination of excellent DC accuracy and
outstanding AC performance. The high-order,
chopper-stabilized modulator achieves very low drift with
low in-band noise. The onboard decimation filter
suppresses modulator and signal out-of-band noise. The
ADS1271 provides a usable signal bandwidth up to 90%
of the Nyquist rate with less than 0.005dB of ripple.
Traditionally, industrial delta-sigma ADCs offering good
drift performance use digital filters with large passband
droop. As a result, they have limited signal bandwidth and
are mostly suited for DC measurements. High-resolution
ADCs in audio applications offer larger usable bandwidths,
but the offset and drift specification are significantly
weaker than their industrial counterparts. The ADS1271
combines these converters, allowing high-precision
industrial measurement with excellent DC and AC
specifications ensured over an extended industrial
temperature range.
Three operating modes allow for optimization of speed,
resolution, and power. A selectable SPI or a frame-sync
serial interface provides for convenient interfacing to
microcontrollers or DSPs. All operations, including internal
offset calibration, are controlled directly by pins; there are
no registers to program.
VREFP VREFN AVDD DVDD
Control
Logic
AINP
AINN
∆Σ
Modulator
Digital
Filter
Serial
Interface
SYNC/PDWN
MODE
CLK
DRDY/FSYNC
SCLK
DOUT
DIN
FORMAT
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
www.ti.com
1 page  
www.ti.com
PIN ASSIGNMENTS
ADS1271
SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004
TSSOP (PW) PACKAGE
(TOP VIEW)
AINP 1
AINN 2
AGND 3
AVDD 4
MODE 5
FORMAT 6
SYNC/PDWN 7
DIN 8
ADS1271
16 VREFP
15 VREFN
14 DGND
13 DVDD
12 CLK
11 SCLK
10 DRDY/FSYNC
9 DOUT
Terminal Functions
NAME
AINP
PIN
NO. FUNCTION
1 Analog Input Positive analog input
DESCRIPTION
AINN
2 Analog Input Negative analog input
AGND
3 Analog Input Analog ground
AVDD
4 Analog Input Analog supply
MODE
5 Digital Input MODE = 0: High-Speed mode
MODE = float: High-Resolution mode
MODE = 1: Low-Power mode
FORMAT
6 Digital Input FORMAT = 0: SPI
FORMAT = 1: Frame-Sync
SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low
DIN 8 Digital Input Data input for daisy-chain operation
DOUT
9 Digital Output Data output
DRDY/FSYNC 10
Digital
If FORMAT = 0 (SPI), then pin 10 = DRDY output
Input/Output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input
SCLK
11 Digital Input Serial clock for data retrieval
CLK 12 Digital Input Master clock
DVDD
13 Digital Input Digital supply
DGND
14 Digital Input Digital ground
VREFN
15 Analog Input Negative reference input
VREFP
16 Analog Input Positive reference input
5
5 Page 
ADS1271
www.ti.com
SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, and VREF = 2.5V, unless otherwise noted.
ABSOLUTE OFFSET DRIFT HISTOGRAM
60
30 Units, Based on
50 20_ C Intervals
GAIN DRIFT HISTOGRAM
15
30 Units, Based on
20_C Intervals
40 10
30
20 5
10
0
1 3 5 7 9 11 13 15 17 19 21
Absolute Offset Drift (µV/_C)
Figure 19
0
Gain Drift (ppm/_ C)
Figure 20
40
30
20
10
0
−10
−20
−30
−40
0
OFFSET POWER−ON WARMUP
Response
Band
High−Speed Mode
DVDD = 3.3V
10 20 30 40 50
Time After Power−On (s)
Figure 21
60
10
8
6
4
2
0
−2
−4
−6
−8
−10
0
GAIN ERROR POWER−ON WARMUP
High−Speed Mode
DVDD = 3.3V
Response
Band
10 20 30 40 50
Time After Power−On (s)
Figure 22
60
UNCALIBRATED OFFSET HISTOGRAM
30
High−Speed Mode
30 Units
20
GAIN ERROR HISTOGRAM
50
High−Speed Mode
30 Units
40
30
20
10
10
00
Uncalibrated Offset (µV)
Figure 23
Gain Error (ppm)
Figure 24
11
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| PDF Descargar | [ Datasheet ADS1271IPWR.PDF ] | |
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