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ADS1252 の電気的特性と機能

ADS1252のメーカーはBurr-Brown Corporationです、この部品の機能は「24-Bit/ 40kHz ANALOG-TO-DIGITAL CONVERTER」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADS1252
部品説明 24-Bit/ 40kHz ANALOG-TO-DIGITAL CONVERTER
メーカ Burr-Brown Corporation
ロゴ Burr-Brown Corporation ロゴ 




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ADS1252 Datasheet, ADS1252 PDF,ピン配置, 機能
®
ADS1252
ADS1252
For most current data sheet and other product
information, visit www.burr-brown.com
24-Bit, 40kHz
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 24 BITS NO MISSING CODES
q 19 BITS EFFECTIVE RESOLUTION UP TO
40kHz DATA RATE
q LOW NOISE: 2.5ppm
q DIFFERENTIAL INPUTS
q INL: 0.0015% (max)
q EXTERNAL REFERENCE
q POWER-DOWN MODE
q SYNC MODE
APPLICATIONS
q CARDIAC DIAGNOSTICS
q DIRECT THERMOCOUPLE INTERFACE
q BLOOD ANALYSIS
q INFRARED PYROMETER
q LIQUID/GAS CHROMATOGRAPHY
q PRECISION PROCESS CONTROL
DESCRIPTION
The ADS1252 is a precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converter with
24-bit resolution operating from a single +5V supply.
The delta-sigma architecture is used for wide dynamic
range and to guarantee 24 bits of no missing code
performance. An effective resolution of 19 bits (2.5ppm
of rms noise) is achieved for conversion rates up to
40kHz.
The ADS1252 is designed for high-resolution mea-
surement applications in cardiac diagnostics, smart
transmitters, industrial process control, weigh scales,
chromatography, and portable instrumentation. The
converter includes a flexible, two-wire synchronous
serial interface for low-cost isolation.
The ADS1252 is a single-channel converter and is
offered in an SO-8 package.
ADS1252
+VIN
–VIN
+
4th-Order
∆Σ
Modulator
Digital
Filter
Serial
Interface
Control
VREF
CLK
SCLK
DOUT/DRDY
+VDD
GND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-1550
Printed in U.S.A. June, 2000

1 Page





ADS1252 pdf, ピン配列
ABSOLUTE MAXIMUM RATINGS
Analog Input: Current ................................................ ±100mA, Momentary
±10mA, Continuous
Voltage ....................................... GND –0.3V to VDD + 0.3V
VDD to GND .............................................................................. –0.3V to 6V
VREF Voltage to GND ................................................. –0.3V to VDD + 0.3V
Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................... –0.3V to VDD + 0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (any package) .................................................. 500mW
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS1252U
"
PACKAGE
SO-8
"
PACKAGE
DRAWING
NUMBER
182
"
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
"
PACKAGE
MARKING
ADS1252U
"
ORDERING
NUMBER(1)
ADS1252U
ADS1252U/2K5
TRANSPORT
MEDIA
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “ADS1252U/2K5” will get a single 2500-piece Tape and Reel.
PIN CONFIGURATION
Top View
SO-8
+VIN 1
–VIN 2
+VDD 3
CLK 4
ADS1252U
8 VREF
7 GND
6 SCLK
5 DOUT/DRDY
PIN DESCRIPTIONS
PIN
NAME
PIN DESCRIPTION
1
+VIN
Analog Input: Positive Input of the Differential Analog Input.
2 –VIN Analog Input: Negative Input of the Differential Analog Input.
3
+VDD
Input: Power Supply Voltage, +5V.
4
CLK
Digital Input: Device System Clock. The system clock is in the form of a CMOS-compatible clock. This is a Schmitt-Trigger input.
5 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. A logic LOW on this output indicates that a new output word is available from the
ADS1252 data output register. The serial data is clocked out of the serial data output shift register using SCLK.
6
SCLK
Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently
from the system clock, therefore, it is possible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW.
Holding SCLK HIGH will either initiate a modulator reset for synchronizing multiple converters or enter power-down mode. This
is a Schmitt-Trigger input.
7
GND
Input: Ground.
8
VREF
Analog Input: Reference Voltage Input.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life-support devices and/or systems.
®
3 ADS1252


3Pages


ADS1252 電子部品, 半導体
THEORY OF OPERATION
The ADS1252 is a precision, high dynamic range, 24-bit,
delta-sigma, A/D converter capable of achieving very high-
resolution digital results at high data rates. The analog input
signal is sampled at a rate determined by the frequency of
the system clock (CLK). The sampled analog input is modu-
lated by the delta-sigma A/D modulator. This is followed by
a digital filter. A sinc5 digital low-pass filter processes the
output of the delta-sigma modulator and writes the result
into the data output register. The DOUT/DRDY pin is pulled
LOW indicating that new data is available to be read by the
external microcontroller/microprocessor. As shown in the
block diagram, the main functional blocks of the ADS1252
are the fourth-order delta-sigma modulator, a digital filter,
control logic, and a serial interface. Each of these functional
blocks is described below.
ANALOG INPUT
The ADS1252 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 100dB, and excellent power supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V when the reference input voltage equals +4.096V.
The bipolar range is with respect to –VIN and not with
respect to GND.
Figure 1 shows the basic input structure of the ADS1252.
The impedance is directly related to the sampling frequency
of the input capacitor which is set by the CLK rate. Higher
CLK rates result in lower impedance and lower CLK rates
result in higher impedance.
RSW
(300typical)
Internal
AIN Circuitry
Modulator Frequency
= fMOD
CINT
(20pF typical)
VCM
FIGURE 1. Analog Input Structure.
The input impedance of the analog input changes with
ADS1252 system clock frequency (CLK). The relationship
is:
AIN Impedance () = (16MHz/CLK) • 19,000
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy. If the source
impedance of the input signal is significant, or if there is
passive filtering prior to the ADS1252, a significant portion
of the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out
of the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth
of the analog input signal must be band limited. The band-
width is a function of the system clock frequency. With a
system clock frequency of 16MHz, the data output rate is
41.667kHz, with a –3dB frequency of 9kHz. The –3dB
frequency scales with the system clock frequency.
To guarantee the best linearity of the ADS1252, a fully
differential signal is recommended.
DELTA-SIGMA MODULATOR
The ADS1252 operates from a nominal system clock fre-
quency of 16MHz. The modulator frequency is fixed in
relation to the system clock frequency. The system clock
frequency is divided by 6 to derive the modulator frequency.
Therefore, with a system clock frequency of 16MHz, the
modulator frequency is 2.667MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modu-
lator is 64, and with the modulator frequency running at
2.667MHz, the data rate is 41.667kHz. Using a slower
system clock frequency will result in a lower data output
rate, as shown in Table I.
CLK (MHz)
DATA OUTPUT RATE (Hz)
16.000(1)
15.360(1)
15.000(1)
14.745600(1)
14.318180(1)
12.288000(1)
12.000000(1)
11.059220(1)
10.000000(1)
9.600000
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
41.667
40,000
30,063
38,400
37,287
32,000
31,250
28,800
26,042
25,000
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
100
60
50
30
25
20
16.67
15
12.50
10
NOTE: (1) Standard Clock Oscillator.
TABLE I. CLK Rate versus Data Output Rate.
®
ADS1252
6

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