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PDF AK4117 Data sheet ( Hoja de datos )
| Número de pieza | AK4117 | |
| Descripción | Low Power 192kHz Digital Audio Receiver | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK4117]
AK4117
Low Power 192kHz Digital Audio Receiver
GENERAL DESCRIPTION
The AK4117 is a S/PDIF AES/EBU receiver supporting sample rates up to 192kHz and resolution up to
24-bit. The integrated channel status decoder supports both consumer and professional modes. The
AK4117 can automatically detect a Non-PCM bit stream. Combining the AK4117 with a multi-channel
codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be
controlled via microprocessor serial interface. A low power mode is available for normal speed modes
and the small 24pin VSOP package saves board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low jitter Analog PLL
PLL Lock Range : 32kHz to 192kHz
Clock Source: PLL or X'tal
2-channel Receiver inputs Selector
Auxiliary digital input
Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error Detection
- Validity Flag Detection
Up to 24bit Audio Data Format
Audio I/F: Left justified, Right justified (16bit, 18bit, 20bit, 24bit), I2S
40-bit Channel Status Buffer
Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
Q-subcode Buffer for CD bit stream
4-wire Serial µP I/F
Master Clock Output: 128fs/256fs/512fs
Operating Voltage: 2.7 to 3.6V
Small Package: 24pin VSOP
Ta: -40 to 85°C
MS0157-E-04
-1-
2010/08
1 page  
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies: Analog
AVDD
-0.3
4.6
Digital
DVDD
-0.3
4.6
|AVSS-DVSS| (Note 3)
ΔGND
0.3
Input Current (Any pins except supplies)
Input Voltage (Except RX0, RX1 pins)
(RX0, RX1 pins)
IIN
VIN1
VIN2
-
-0.3
-0.3
±10
DVDD+0.3
AVDD+0.3
Ambient Temperature (Power applied)
Ta -40
85
Storage Temperature
Tstg -65
150
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
[AK4117]
Units
V
V
V
mA
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
2.7
3.3
Digital
DVDD
2.7
3.3
Note 2. All voltages with respect to ground.
max
3.6
AVDD
Units
V
V
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.7~3.6V)
Parameter
Symbol
min
typ
Input Resistance
Zin - 10
Input Voltage
VTH
350
Input Sample Frequency
fs 32 -
max Units
- kΩ
mVpp
192 kHz
DC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.7~3.6V; unless otherwise specified)
Parameter
Symbol
min
typ
max
Power Supply Current
Normal operation (PDN= “H”) (Note 4)
LP= “0”, CM1-0= “00”
(Note 5)
14 28
LP= “1”, CM1-0= “00”
(Note 6)
7 14
LP= “1”, CM1-0= “01”
(Note 7)
2-
Power down (PDN = “L”)
(Note 8)
10 100
High-Level Input Voltage
VIH 70%DVDD - DVDD+0.3
Low-Level Input Voltage
VIL DVSS-0.3
- 30%DVDD
High-Level Output Voltage
Low-Level Output Voltage
(Iout=-400μA)
(Iout=400μA)
VOH
VOL
DVDD-0.4
-
-
-
-
0.4
Input Leakage Current
Iin -
- ± 10
Note 4. AVDD=DVDD=3.3V.
Note 5. fs=192kHz, X'tal=24.576MHz, PCKS1-0= “10” , CL=20pF. AVDD=5mA (typ), DVDD=9mA (typ).
Note 6. fs=48kHz, X'tal=24.576MHz, CL=20pF. AVDD=4mA (typ), DVDD=3mA (typ).
Note 7. fs=48kHz, X'tal=24.576MHz. The external load current is not included.
Note 8. RX inputs are open and all digital input pins are held at DVDD or DVSS.
Units
mA
mA
mA
μA
V
V
V
V
μA
MS0157-E-04
-5-
2010/08
5 Page 
[AK4117]
■ Master Clock Output
The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as shown
in Table 2. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs, MCKO goes to
“L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In low power mode, PLL
lock range is up to 48kHz and the MCKO frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit selects
the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 3).
LP
PCKS1
PCKS0
MCKO
fs [kHz]
0
0
512fs
32 ∼ 48
0
0
1
1
256fs
32 ∼ 96
0
128fs
32 ∼ 192
1 1 N/A N/A
1
x
x
256fs
32 ∼ 48 Default
Table 2. Master Clock Frequency Select
(PLL mode: Clock operation mode 0, 2(UNLCK=0))
XCKS1
0
0
1
1
XCKS0
0
1
0
1
X’tal
or
EXT
128fs
256fs
512fs
1024fs
MCKO
DIV=0
128fs
256fs
512fs
1024fs
DIV=1
64fs
128fs
256fs
512fs
fs [kHz]
EXTCLK [MHz]
2.048
16
8
N/A
N/A
4.096
32
16
8
N/A
8.192
64
32
16
8
X’tal [MHz]
11.2896 12.288 24.576
88.2 96 192
44.1 48
96
N/A N/A
48
N/A N/A N/A
Default
Table 3. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3)
MS0157-E-04
- 11 -
2010/08
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4117.PDF ] | |
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