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ADV7196A の電気的特性と機能

ADV7196AのメーカーはAnalog Devicesです、この部品の機能は「Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs/ 10-Bit Data Input/ and Macrovision」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7196A
部品説明 Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs/ 10-Bit Data Input/ and Macrovision
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7196A Datasheet, ADV7196A PDF,ピン配置, 機能
a
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs,
10-Bit Data Input, and Macrovision
ADV7196A
FEATURES
INPUT FORMATS
YCrCb in 2 ؋ 10-Bit (4:2:2) or 3 ؋ 10-Bit (4:4:4) Format
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p) and
Any Other High Definition Standard Using Async
Timing Mode
RGB in 3 ؋ 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit and Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (؎)
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2؋ Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
I2C® Filter
VBI Open Control
Macrovision Rev. 1.0 (525p)
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
DVD Players
MPEG 2 at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7196A is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
FUNCTIONAL BLOCK DIAGRAM
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
CGMS
MACROVISION
TEST PATTERN
GENERATOR
AND
DELAY
AND
GAMMA
CORRECTION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
CHROMA
4:2:2
TO
4:4:4
(SSAF)
LUMA
SSAF
2؋ INTER-
POLATION
ADV7196A
11-BIT+
SYNC
DAC
11-BIT
DAC
11-BIT
DAC
TIMING
GENERATOR
SYNC
GENERATOR
I2C MPU
PORT
DAC CONTROL
BLOCK
DAC A (Y)
DAC B
DAC C
VREF
RESET
COMP
The ADV7196A has three separate 10-bit-wide input ports which
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE 293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can be
used to input data to the ADV7196A. For all standards, external
horizontal, vertical, and blanking signals or EAV/SAV codes control
the insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
The ADV7196A outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7196A requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used, allows
removal of ringing on the incoming Y data. The ADV7196A
supports CGMS-A data control generation and the Macrovision
Anticopy algorithm in 525p mode.
The ADV7196A is packaged in a 52-lead MQFP package.
I2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

1 Page





ADV7196A pdf, ピン配列
ADV7196A
ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . . 23
AFG3 (AFG3)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . . 23
AFTA (AFTA)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . . 23
AFTB (AFTB)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . . 23
AFTC (AFTC)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . 24
Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . . 24
Adaptive Filter Control Application . . . . . . . . . . . . . . . . . 25
HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
HEXMR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 26
Output Standard Selection (MR00–MR01) . . . . . . . . . . . 26
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . . 26
Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 27
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 27
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reserved (MR15–MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 27
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 28
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR26–MR27) . . . . . . . . . . . . . . . . . . . . . . . . . 28
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 28
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR36–MR37) . . . . . . . . . . . . . . . . . . . . . . . . . 28
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR54–MR57) . . . . . . . . . . . . . . . . . . . . . . . . . 29
DAC TERMINATION AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31
Video Output Buffer and Optional Output Filter . . . . . . . 31
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36
REV. 0
–3–


3Pages


ADV7196A 電子部品, 半導体
ADV7196A
CLOCK
t9 t10
R0
R1
R2
•••
•••
Rxxx
Rxxx
PIXEL INPUT
DATA
G0
G1 G2
G3
•••
Gxxx
Gxxx
B0
B1 B2
B3
•••
Bxxx
Bxxx
t12
t11
t9 CLOCK HIGH TIME
t10 CLOCK LOW TIME
t11 DATA SETUP TIME
t12 DATA HOLD TIME
Figure 1. 4:4:4 RGB Input Data Format Timing Diagram
CLOCK
t9 t10
Y0
Y1
Y2
•••
•••
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0 Cr0 Cb1 Cr1
t12
t11
•••
Cbxxx
Crxxx
t9 CLOCK HIGH TIME
t10 CLOCK LOW TIME
t11 DATA SETUP TIME
t12 DATA HOLD TIME
Figure 2. 4:2:2 Input Data Format Timing Diagram
CLOCK
t9 t10
Y0
Y1
Y2
•••
•••
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0
Cb1 Cb2
Cb3
•••
Cbxxx
Cbxxx
Cr0
Cr1 Cr2
Cr3
•••
Crxxx
Crxxx
t12
t11
t9 CLOCK HIGH TIME
t10 CLOCK LOW TIME
t11 DATA SETUP TIME
t12 DATA HOLD TIME
Figure 3. 4:4:4 YCrCb Input Data Format Timing Diagram
–6– REV. 0

6 Page



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部品番号部品説明メーカ
ADV7196A

Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs/ 10-Bit Data Input/ and Macrovision

Analog Devices
Analog Devices


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