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ADV7181 の電気的特性と機能

ADV7181のメーカーはAnalog Devicesです、この部品の機能は「Multiformat SDTV Video Decoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7181
部品説明 Multiformat SDTV Video Decoder
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7181 Datasheet, ADV7181 PDF,ピン配置, 機能
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™)
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and Betacam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
GENERAL DESCRIPTION
The ADV7181 integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The six analog input channels accept standard composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
Multiformat SDTV Video Decoder
ADV7181
Differential phase: 0.6° typ
Programmable video controls:
Peak-white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free run mode (generates stable video ouput with no I/P)
VBI decode support for
Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receiver
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allow very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181 modes
are set up over a 2-wire, serial, bidirectional port (I2C-
compatible).
The ADV7181 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181 is packaged in a small 64-lead LFCSP and LQFP
and Pb-free packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.

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ADV7181 pdf, ピン配列
REVISION HISTORY
3/05—Rev. A to Rev. B
Changes to the Analog Specifications Section ..............................8
Changes to Table 20 and Table 21 ................................................17
Changes to Table 27 and Table 28 ................................................19
Change to Table 50..........................................................................25
Addition to the Clamp Operation Section...................................26
Changes to Figures 11.....................................................................29
Changes to Figures 12, 13, 14 ........................................................30
Changes to Chroma Filter Section ................................................30
Deleted YPM Section and Renumbered Subsequent Tables .....30
Changes to Figure 15 ......................................................................31
Change to the Luma Gain Section ................................................32
Changes to Table 103 and Table 104............................................42
Deleted Table 172 and Renumbered Subsequent Tables............68
Changes to Table 176......................................................................71
Changes to Table 185......................................................................78
Changes to Table 192......................................................................83
Changes to Table 193......................................................................84
Changes to Table 194......................................................................85
Added XTAL and Load Capacitor Value Selection Section ......97
Change to Figure 41 ........................................................................98
ADV7181
7/04—Rev. 0 to Rev. A
Addition to Applications List ..........................................................1
Changes to Table 3 ............................................................................8
Changes to Table 5 ............................................................................8
Replaced Figure 3 ..............................................................................9
Changes to Global Pin Control Section .......................................16
Changes to Table 202 ......................................................................91
Changes to Table 203 ......................................................................92
Added package in Outline Dimensions Section .......................103
Changes to Ordering Guide.........................................................104
5/04—Revision 0: Initial Version
Rev. B | Page 3 of 104


3Pages


ADV7181 電子部品, 半導体
ADV7181
SPECIFICATIONS
Temperature range: TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless
otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS1
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Power-Up Time
Symbol
N
INL
DNL
VIH
VIL
IIN
CIN
VOH
VOL
ILEAK
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
IPWRDN
tPWRUP
Test Conditions
BSL at 54 MHz
BSL at 54 MHz
Pin 29
All other pins
ISOURCE = 0.4 mA
ISINK = 3.2 mA
CVBS input2
YPrPb input3
Min Typ
Max
–0.475/+0.6
–0.25/+0.5
9
–1.5/+2
–0.7/+2
2
0.8
–50 +50
–10 +10
10
2.4
0.4
10
20
1.65 1.8
3.0 3.3
1.65 1.8
3.15 3.3
80
2
10.5
85
180
1.5
20
2
3.6
2.0
3.45
Unit
Bits
LSB
LSB
V
V
µA
µA
pF
V
V
µA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
1 Guaranteed by characterization.
2 ADC1 and ADC2 powered down.
3 All three ADCs powered on.
Rev. B | Page 6 of 104

6 Page



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共有リンク

Link :


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