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AT892051 の電気的特性と機能

AT892051のメーカーはATMEL Corporationです、この部品の機能は「8-Bit Microcontroller with 2K Bytes Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT892051
部品説明 8-Bit Microcontroller with 2K Bytes Flash
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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AT892051 Datasheet, AT892051 PDF,ピン配置, 機能
Features
Compatible with MCS-51™ Products
2K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
2.7V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Two-Level Program Memory Lock
128 x 8-Bit Internal RAM
15 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial UART Channel
Direct LED Drive Outputs
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
2K Bytes of Flash programmable and erasable read only memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set. By combining
a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a pow-
erful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.
The AT89C2051 provides the following standard features: 2K Bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-
tion down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The Power Down Mode saves the
RAM contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.
8-Bit
Microcontroller
with 2K Bytes
Flash
AT89C2051
Pin Configuration
PDIP/SOIC
/VPP
0368D-B–12/97
4-15

1 Page





AT892051 pdf, ピン配列
AT89C2051
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to
P1.7 provide internal pullups. P1.0 and P1.1 require exter-
nal pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the
on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (IIL) because
of the internal pullups.
Port 1 also receives code data during Flash programming
and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C2051 as listed below:
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine cycles
while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Figure 1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
4-17


3Pages


AT892051 電子部品, 半導体
Programming The Flash
The AT89C2051 is shipped with the 2K bytes of on-chip
PEROM code memory array in the erased state (i.e., con-
tents = FFH) and ready to be programmed. The code mem-
ory array is programmed one byte at a time. Once the array
is programmed, to re-program any non-blank byte, the
entire memory array needs to be erased electrically.
Internal Address Counter: The AT89C2051 contains an
internal PEROM address counter which is always reset to
000H on the rising edge of RST and is advanced by apply-
ing a positive going pulse to pin XTAL1.
Programming Algorithm: To program the AT89C2051,
the following sequence is recommended.
1. Power-up sequence:
Apply power between VCC and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to ’H’
Set pin P3.2 to ’H’
3. Apply the appropriate combination of ’H’ or ’L’ logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the
programming operations shown in the PEROM Pro-
gramming Modes table.
To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to
P1.7.
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array
or the lock bits. The byte-write cycle is self-timed and
typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to
logic ’H’ level and set pins P3.3 to P3.7 to the appropiate
levels. Output data can be read at the port P1 pins.
8. To program a byte at the next address location, pulse
XTAL1 pin once to advance the internal address counter.
Apply new data to the port P1 pins.
9. Repeat steps 5 through 8, changing data and advancing
the address counter for the entire 2K bytes array or until
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to ’L’
set RST to ’L’
Turn VCC power off
Data Polling: The AT89C2051 features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P1.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also
be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indi-
cate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
for verification:
1. Reset the internal address counter to 000H by bringing
RST from ’L’ to ’H’.
2. Apply the appropriate control signals for Read Code data
and read the output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address
counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are
enabled.
Chip Erase: The entire PEROM array (2K bytes) and the
two Lock Bits are erased electrically by using the proper
combination of control signals and by holding P3.2 low for
10 ms. The code array is written with all “1”s in the Chip
Erase operation and must be executed before any non-
blank memory byte can be re-programmed.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 001H, and 002H, except that P3.5 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 21H indicates 89C2051
Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combi-
nation of control signals. The write operation cycle is self-
timed and once initiated, will automatically time itself to
completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
4-20 AT89C2051

6 Page



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部品番号部品説明メーカ
AT892051

8-Bit Microcontroller with 2K Bytes Flash

ATMEL Corporation
ATMEL Corporation


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