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PDF BS62LV2005 Data sheet ( Hoja de datos )
| Número de pieza | BS62LV2005 | |
| Descripción | Very Low Power/Voltage CMOS SRAM 256K X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
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Hay una vista previa y un enlace de descarga de BS62LV2005 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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BSI Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BS62LV2005
FEATURES
• Wide Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns(Max.) at Vcc = 5.0V
-55 55ns(Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
DESCRIPTION
The BS62LV2005 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.6uA and maximum access time of 55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2005 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2005 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV2005TC
BS62LV2005STC
BS62LV2005SC
BS62LV2005TI
BS62LV2005STI
BS62LV2005SI
+0 O C to +70O C 4.5V ~ 5.5V
-40 O C to +85O C 4.5V ~ 5.5V
SPEED
(ns)
Vcc=5.0V
55 / 70
55 / 70
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC , Max)
Vcc=5.0V
Vcc=5.0V
6uA 35mA
25uA
40mA
PKG TYPE
TSOP -32
STSOP-32
SOP -32
TSOP -32
STSOP-32
SOP -32
PIN CONFIGURATIONS
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV2005TC
BS62LV2005STC
BS62LV2005TI
BS62LV2005STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 BS62LV2005SC 26
8 BS62LV2005SI 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
BLOCK DIAGRAM
A13
A17
A15
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
2048
8 Column I/O
Write Driver
Sense Amp
8
256
Column Decoder
16
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV2005
1
Revision 2.4
April 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
t OH
t AA
t RC
BS62LV2005
t OH
READ CYCLE2 (1,3,4)
CE1
t ACS1
CE2
D OUT
READ CYCLE3 (1,4)
ADDRESS
OE
CE1
CE2
D OUT
t ACS2
t (5)
CLZ
t RC
t AA
t OE
t OLZ
t ACS1
t (5)
CLZ1
t ACS2
t (5)
CLZ2
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
t , tCHZ1
(5)
CHZ2
t OH
t (5)
OHZ
t (1,5)
CHZ1
t (2,5)
CHZ2
R0201-BS62LV2005
5
Revision 2.4
April 2002
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet BS62LV2005.PDF ] | |
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