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IXDP630PI の電気的特性と機能

IXDP630PIのメーカーはIXYSです、この部品の機能は「Inverter Interface and Digital Deadtime Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 IXDP630PI
部品説明 Inverter Interface and Digital Deadtime Generator
メーカ IXYS
ロゴ IXYS ロゴ 




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IXDP630PI Datasheet, IXDP630PI PDF,ピン配置, 機能
Inverter Interface and Digital Deadtime Generator
for 3-Phase PWM Controls
Type
IXDP630 PI
IXDP631 PI
Package
18-Pin Plastic DIP
18-Pin Plastic DIP
Configuration
RC Oscillator
Crystal Oscillator
Temp. Range
-40°C to +85°C
-40°C to +85°C
This 5 V HCMOS integrated circuit is
intended primarily for application in
three-phase, sinusoidally commutated
brushless motor, induction motor, AC
servomotor or UPS PWM modulator
control systems. It injects the required
deadtime to convert a single phase leg
PWM command into the two separate
logic signals required to drive the upper
and lower semiconductor switches in a
PWM inverter. It also provides facilities
for output disable and fast overcurrent
and fault condition shutdown.
In the IXDP630, deadtime programming
is achieved by an internal RC oscillator.
In the IXDP631, programming is
achieved by use of a crystal oscillator.
An alternative for both the IXDP630/
631 is with an external clock signal.
Because of its flexibility, the IXDP630/
631 is easily utilized in a variety of
brushed DC, trapezoidally commutated
brushless DC, hybrid and variable
reluctance step and other more exotic
PWM motor drive power and control
circuit designs.
Block Diagram IXDP 630/IXDP 631
Features
l 5 V HCMOS logic implementation
maintains low power at high speed
l Schmitt trigger inputs and CMOS
logic levels improve noise immunity
l Simultaneously injects equal dead-
time in up to three output phases
l Replaces 10-12 standard SSI/MSI
logic devices
l Allows a wide range of PWM
modulation strategies
l Directly drives high speed
optocouplers
Applications
l 1- and 3- Phase Motion Controls
l 1- and 3- Phase UPS Systems
l General Power Conversion Circuits
l Pulse Timing and Waveform
Generation
l General Purpose Delay and Filter
l General Purpose Three Channel
"One Shot"
IXYS reserves the right to change limits, test conditions and dimensions.
I - 14
© 1998 IXYS All rights reserved

1 Page





IXDP630PI pdf, ピン配列
Pin Description IXDP630
Pin Description IXDP631
IXDP630
IXDP631
Sym. Pin Description
R 1 R, S and T are the three single-
S 3 phase inputs. Each input is
T 5 expanded into two outputs to
generate non-overlapping drive
signals, RU/RL, SU/SL, and TU/
TL. The delay from the falling
edge of one line to the rising
edge of the other is a function of
the clock.
ENAR 2
ENAS 4
ENAT 6
High logic input will enable the
outputs, as set by the proper
input phase. The ENA (R,S,T)
signals control the drive output
lines. A low logic input will force
both controlled outputs to a low
logic level
OUT
ENA
7 High logic level will enable all
outputs to their related phase.
The OUTENA simultaneously
controls all outputs. Low input
logic level will inhibit all outputs
(low).
RESET 8
The RESET signal is active low.
When a logic low RESET is
applied, all outputs will go low.
After releasing the RESET
command within the generated
delay, the outputs will align with
the phase input level after the
programmed delay internal.
Sym. Pin Description
GND 9 CIRCUIT GROUND - 0 Volts
RCIN 10 The first node of the clock
or network. For the IXDP630, the
XTLIN RC input is applied to RCIN. For
the IXDP 631, the crystal oscil-
lator is applied to XTLIN. If an
external clock is to be supplied
to the chip it should be connec-
ted to this pin.
OSC
OUT
11 This is the output node of the
oscillator. It is connected indi-
rectly to the RCIN or XTLIN pins
when using the internal oscillator
as described in the applications
information. It is not recommen-
ded for external use.
TL 12 After the appropriate delay, the
TU 13 external drive outputs (R,S, T) U
SL 14 are in phase with their corres-
SU 15 ponding inputs; (R,S, T) L are
RL 16 the complementary outputs.
RU 17
VCC 18 Voltage Supply +5 V ± 10 %
Waveforms
deadtime
deadtime
Note: X = Any input, R, S or T.
deadtime
I - 16
deadtime
deadtime
noise
deadtime
This diagram shows the normal
operation of the IXDP630/631 after the
RESET input is released. The
DEADTIME is the 8 Clock periods
between XU and XL when both XU and
XL are a "0". The length of the
DEADTIME is fixed at 8 times the
period of CLK.
The diagram shows OUTENA and ENAX
asynchronously forcing the XU Output
and the XL Output to the off state.
OUTENA will force all three channels to
the off state. ENAX (where X is one of
the three channels) will only force the
XU and XL Outputs of that channel to
the off state. Note that because ENAX
is asynchronous with respect to the
internal clock and deadtime counters,
when ENAX goes HI whatever state the
deadtime counter was in immediately
propagates to the output. This figure
also shows that noise at the XIN input
will be filtered before the XU Output or
XL Output will become active, which
may extend the deadtime.
© 1998 IXYS All rights reserved


3Pages


IXDP630PI 電子部品, 半導体
IXDP630
IXDP631
IXDP630 RC Oscillator Component
Details
The IXDP630 oscillator has only two
external components. Rosc should be
a precision, high frequency resistor.
The material used in carbon compo-
sition resistors is hydroscopic (it
absorbs water), causing resistors
above 100 kto 1 Mto change value
with relative humidity. This is on top of
initial tolerance and temperature
coefficient deviations, and so is not
recommended. Instead, precision
metal film or carbon film resistor
construction is preferred, with initial
tolerances of 1 % and better with
temperature coefficients of ±100 ppm.
The construction of Cosc is also critical
to circuit operation. Cosc should be a
good quality monolithic ceramic (single
or multilayer) or a metallized polypropy-
lene timing capacitor. If ceramic techno-
logy is chosen, be sure to consider
temperature coefficient and tolerance. It
is the minimum capacitor value that is
critical, not the part number rated
capacitance. A Z5U ceramic has an
initial tolerance of +80/-20 %, and a
temperature variation of +30/-80 %
over temperature. An X7R is ±10 %
initial tolerance, ±10 % over
temperature. An NPO is ±5 % initial
tolerance, ±5 % over temperature
(although tighter selections are readily
available in NPO).
If film technology is chosen, polypropy-
lene is one of the best choices.
Tolerances down to 1 % and 2 % are
standard and temperature coefficient is
±100 ppm.
The layout of the external components
is also critical. The components should
be as close to the device as possible,
minimizing stray capacitance and
inductance.
Fig. 5. Recommended Crystal
Oscillator Components
© 1998 IXYS All rights reserved
IXDP631 Crystal Oscillator
Component Details
The IXDP631 oscillator requires three
external passive components, in
addition to the crystal. The crystal is
chosen with a frequency below fclk
(min). The capacitors and resistor
(illustrated earlier in Fig. 5) follow rules
similar to the RC oscillator option. The
resistor should be metal or carbon film,
although its accuracy and stability do
not significantly affect oscillator
frequency accuracy. The capacitors
should be monolithic ceramic
construction (CK05, or similar) with
X7R or better characteristics.
Grounding, Interfacing and Noise
Immunity
Due to the very high level of currents
that are switched at high speed in a
typical motor control power circuit,
voltage transients (V = L • di/dt) can
cause serious problems. Fast digital
circuits respond to transients instead of
legitimate inputs, disturbing inverter
operation or causing outright failure.
Bypassing and Decoupling
As with any high speed logic compo-
nent, the IXDP630/631 should be
bypassed with a good quality (mono-
lithic ceramic or film) capacitor designed
specifically for bypass application.
Decoupling is normally not required.
The IXDP630 does not generate
sufficient supply line current ripple to be
a significant noise source when
properly bypassed, and it is capable of
rejecting normal supply line noise.
Logic Levels
All inputs to the IXDP630 and IXDP631
(except XTLIN on the IXDP631) are
HCMOS Schmitt Trigger compatible.
On the IXDP631, the XTLIN pin is
different because the crystal oscillator
circuit cannot tolerate a Schmitt input.
The hysteresis inherent in Schmitt
Trigger inputs greatly improves the
reliability of digital communications. It
can reject ground bounce of up to 2 V,
and induced voltages in digital signal
traces of 1 V.
Power Circuit Noise Generation
In a typical transistor inverter, the
output MOSFET may switch on or off
with di/dt 500A/µs. Referring to Fig. 6,
and assuming that the MOSFET
Source Terminal has a 1 inch path on
the PCB to system ground, a voltage as
high as 13.5 V can be developed:
V = 27 nH • 500A/µs = 13.5 V
If the MOSFET switches 25 A, the
transient will last as long as (25/500) µs
or 50 ns, which is much more than the
typical 6 or 7 ns propagation delay of a
74 HC series gate.
Caution: If one set of digital circuits is
tied to system ground, and one to local
ground, it is clear that such a transient
would cause spurious outputs. In an
inverter, the consequences of such an
error could be catastrophic. Turning a
transistor on at the wrong time could
easily cause it to explode, with the
potential for equipment damage and
operator injury -- clearly undesirable.
Fig. 6. Power circuit noise generation
Methods of Correcting these
Problems
The first step is to use a logic family
with inherent noise immunity. Standard
TTL (or any of its derivatives, including
74HCT CMOS) is a poor choice
because of the logic levels these fami-
lies employ. In particular, VOL, VIL are too
close to ground to reject the levels of
ground noise common to power circuits.
74HC logic is significantly superior, and
the older 4000 series CMOS is even
better. Unfortunately, in modern motor
controls, especially those that employ
microprocessors, the speeds of the
4000 series CMOS are no longer
adequate. In most cases 74HC logic is
the only viable alternative.
Layout
The second, and most important step is
the printed circuit board (PCB) layout.
The PCB is a very important compo-
nent in any power circuit, and there is a
I - 19

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部品番号部品説明メーカ
IXDP630PI

Inverter Interface and Digital Deadtime Generator

IXYS
IXYS


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