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M28C64X の電気的特性と機能

M28C64XのメーカーはSTMicroelectronicsです、この部品の機能は「64 Kbit (8Kb x8) Parallel EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 M28C64X
部品説明 64 Kbit (8Kb x8) Parallel EEPROM
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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M28C64X Datasheet, M28C64X PDF,ピン配置, 機能
M28C64C
M28C64X
64 Kbit (8Kb x8) Parallel EEPROM
FAST ACCESS TIME: 150ns
SINGLE 5V ± 10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE
– 32 Bytes Page Write Operation
– Byte or Page Write Cycle: 5ms
ENHANCED END OF WRITE DETECTION
– Ready/Busy Open Drain Output
(for M28C64C product only)
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
28
1
PDIP28 (P)
28
1
SO28 (MS)
300 mils
PLCC32 (K)
TSOP28 (N)
8 x13.4mm
DESCRIPTION
The M28C64C is an 8 Kbit x8 low power Parallel
EEPROM fabricated with STMicroelectronics pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 5V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshakingmode with Ready/Busy,
Data Polling and Toggle Bit. The M28C64C sup-
ports 32 byte page write operation.
Figure 1. Logic Diagram
VCC
13
A0-A12
8
DQ0-DQ7
Table 1. Signal Names
A0 - A12 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
VCC Supply Voltage
VSS Ground
W M28C64C
E
RB
G
VSS
AI00746B
February 1999
1/15

1 Page





M28C64X pdf, ピン配列
M28C64C, M28C64X
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
– 40 to 125
°C
T STG
Storage Temperature Range
– 65 to 150
°C
VCC Supply Voltage
– 0.3 to 6.5
V
VIO Input/Output Voltage
– 0.3 to VCC +0.6
V
VI Input Voltage
– 0.3 to 6.5
V
VESD Electrostatic Discharge Voltage (Human Body model)
2000
V
Note: Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Operating Modes
Mode
Read
Write
Standby / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Note: X = VIH or VIL
E GW
VIL VIL VIH
VIL VIH VIL
VIH X
X
X X VIH
X VIL X
X VIH X
DQ0 - DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
Data In/ Out (DQ0 - DQ7). Data is written to or read
from the M28C64C through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the M28C64C.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset (POR) circuit resets all internal programming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specified in Table 6.
Read
The M28C64C is accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pins are high impedancewhen either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28C64C supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A5 - A12 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data up to a maxi-
mum of 100µs after the rising edge of E or W which
ever occurs first (tBLC). If a transition of E or W is
not detected within 100µs, the internal program-
ming cycle will start.
3/15


3Pages


M28C64X 電子部品, 半導体
M28C64C, M28C64X
Table 8. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C, VCC = 4.5V to 5.5V)
Symbol Alt
Parameter
Test Condition
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL
tEHQZ (1)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
-150
min max
150
150
75
0 50
0 50
0
M28C64C
-200
min max
200
200
100
0 60
0 60
0
-250
min max
250
250
110
0 65
0 65
0
Unit
ns
ns
ns
ns
ns
ns
Figure 7. Read Mode AC Waveforms
A0-A12
E
G
DQ0-DQ7
Note: Write Enable (W) = High
tAVQV
VALID
tAXQX
tGLQV
tEHQZ
tELQV
DATA OUT
tGHQZ
Hi-Z
AI00749B
6/15

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
M28C64

64 Kbit (8K x 8) Parallel EEPROM

STMicroelectronics
STMicroelectronics
M28C64C

64 Kbit (8Kb x8) Parallel EEPROM

STMicroelectronics
STMicroelectronics
M28C64X

64 Kbit (8Kb x8) Parallel EEPROM

STMicroelectronics
STMicroelectronics


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