|
|
PDF M28R400CB Data sheet ( Hoja de datos )
| Número de pieza | M28R400CB | |
| Descripción | 4 Mbit 1.8V Supply Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M28R400CB (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
M28R400CT
M28R400CB
4 Mbit (256Kb x16, Boot Block)
1.8V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
– VDD = 1.65V to 2.2V Core Power Supply
– VDDQ= 1.65V to 2.2V for Input/Output
– VPP = 12V for fast Program (optional)
■ ACCESS TIMES: 90ns, 120ns
■ PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ MEMORY BLOCKS
– Parameter Blocks (Top or Bottom
location)
– Main Blocks
■ BLOCK LOCKING
– All blocks locked at Power Up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■ SECURITY
– 64 bit user Programmable OTP cells
– 64 bit unique device identifier
– One Parameter Block Permanently
Lockable
■ AUTOMATIC STAND-BY MODE
■ PROGRAM and ERASE SUSPEND
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28R400CT: 882Ah
– Bottom Device Code, M28R400CB:
882Bh
Figure 1. Package
FBGA
TFBGA46 (ZB)
6.39 x 6.37mm
June 2004
1/48
1 page  
M28R400CT, M28R400CB
SUMMARY DESCRIPTION
The M28R400C is a 4 Mbit (256Kbit x 16) non-vol-
atile Flash memory that can be erased electrically
at the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (1.65 to
2.2V) supply. VDDQ allows to drive the I/O pin
down to 1.65V. An optional 12V VPP power supply
is provided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28R400C has an array of 15
blocks: 8 Parameter Blocks of 4 KWord and 7
Main Blocks of 32 KWord. M28R400CT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28R400CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 4., Block Ad-
dresses.
The M28R400C features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and block
erase. When VPP ≤ VPPLK all blocks are protected
against program or block erase. All blocks are
locked at power-up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divid-
ed into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the us-
er. The user programmable segment can be per-
manently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 5., shows the Security Block
Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The memory is offered in a TFBGA46 (0.75mm
pitch) package and is supplied with all the bits
erased (set to ’1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
18
A0-A17
W
E
G
RP
WP
16
DQ0-DQ15
M28R400CT
M28R400CB
VSS
AI04392
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ15 Data Input/Output
E Chip Enable
G Output Enable
W Write Enable
RP Reset
WP Write Protect
VDD Core Power Supply
VDDQ
Power Supply for
Input/Output
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS Ground
NC Not Connected Internally
5/48
5 Page 
M28R400CT, M28R400CB
pears to start but will terminate, leaving the data
unchanged. No error condition is given when pro-
tected blocks are ignored.
During the erase operation the memory will only
accept the Read Status Register command. All
other commands will be ignored, including the
Erase Suspend command. It is not possible to is-
sue any command to abort the operation.
Chip Erase commands should be limited to a max-
imum of 100 Program/Erase cycles. After 100 Pro-
gram/Erase cycles the internal algorithm will still
operate properly but some degradation in perfor-
mance may occur.
Typical chip erase times are given in Table 7.
Program Command
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 7., Program, Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See APPENDIX C., Figure 15., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Double Word Program Command
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when VPP is not at VPPH. The command can be
executed if VPP is below VPPH but the result is not
guaranteed.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 16., Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron-
ic Signature and Read CFI Query commands. Ad-
ditionally, if the suspend operation was Erase then
the Program, Block Lock, Block Lock-Down or
Protection Program commands will also be ac-
cepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protec-
tion Program commands. When the Program/
Erase Resume command is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to VIH. Program/Erase is aborted if
Reset turns to VIL.
See APPENDIX C., Figure 17., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 19., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister.
See APPENDIX C., Figure 17., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
11/48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M28R400CB.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M28R400CB | 4 Mbit 1.8V Supply Flash Memory | STMicroelectronics |
| M28R400CT | 4 Mbit 1.8V Supply Flash Memory | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |