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DT28F016SA の電気的特性と機能

DT28F016SAのメーカーはIntelです、この部品の機能は「16-MBIT MEMORY」です。


製品の詳細 ( Datasheet PDF )

部品番号 DT28F016SA
部品説明 16-MBIT MEMORY
メーカ Intel
ロゴ Intel ロゴ 




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DT28F016SA Datasheet, DT28F016SA PDF,ピン配置, 機能
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28F016SA 16-MBIT
(1 MBIT X 16, 2 MBIT X 8)
FlashFile™ MEMORY
Includes Commercial and Extended Temperature Specifications
n User-Selectable 3.3V or 5V VCC
n User-Configurable x8 or x16 Operation
n 70 ns Maximum Access Time
n 28.6 MB/sec Burst Write Transfer Rate
n 1 Million Typical Erase Cycles per
Block
n 56-Lead, 1.2 mm x 14 mm x 20 mm
TSOP Package
n 56-Lead, 1.8 mm x 16 mm x 23.7 mm
SSOP Package
n Revolutionary Architecture
Pipelined Command Execution
Program during Erase
Command Superset of Intel
28F008SA
n 1 mA Typical ICC in Static Mode
n 1 µA Typical Deep Power-Down
n 32 Independently Lockable Blocks
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.
The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read
performance and selective block locking provide highly flexible memory components suitable for Resident
Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage
enables the design of memory cards which can be interchangeably read/written in 3.3V and 5.0V systems. Its
x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and
flexible block locking enable both storage and execution of operating systems and application software.
Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,
highest density monolithic 3.3V FlashFile memory.
November 1996
Order Number: 290489-004

1 Page





DT28F016SA pdf, ピン配列
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28F016SA
CONTENTS
PAGE
1.0 INTRODUCTION ............................................. 5
1.1 Product Overview ........................................ 5
2.0 DEVICE PINOUT............................................. 6
2.1 Lead Descriptions ........................................ 8
3.0 MEMORY MAPS ........................................... 12
3.1 Extended Status Register Memory Map..... 13
4.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS............. 14
4.1 Bus Operations for Word-Wide Mode
(BYTE# = VIH)........................................... 14
4.2 Bus Operations for Byte-Wide Mode
(BYTE# = VIL) ........................................... 14
4.3 28F008SA–Compatible Mode Command
Bus Definitions.......................................... 15
4.4 28F016SA–Performance Enhancement
Command Bus Definitions......................... 16
4.5 Compatible Status Register ....................... 18
4.6 Global Status Register ............................... 19
4.7 Block Status Register ................................ 20
5.0 ELECTRICAL SPECIFICATIONS ................. 21
5.1 Absolute Maximum Ratings ....................... 21
5.2 Capacitance............................................... 22
5.3 Timing Nomenclature................................. 23
5.4 DC Characteristics (VCC = 3.3V ± 10%) ..... 26
5.5 DC Characteristics
(VCC = 5.0V ± 10%, 5.0V ± 5%) ................ 29
PAGE
5.6 AC Characteristics–Read Only
Operations.................................................32
5.7 Power-Up and Reset Timings.....................37
5.8 AC Characteristics for WE#–Controlled
Command Write Operations ......................38
5.9 AC Characteristics for CE#–Controlled
Command Write Operations ......................42
5.10 AC Characteristics for Page Buffer Write
Operations.................................................46
5.11 Erase and Word/Byte Program
Performance, Cycling Performance and
Suspend Latency.......................................49
6.0 DERATING CURVES.....................................50
7.0 MECHANICAL SPECIFICATIONS FOR
TSOP ............................................................52
8.0 MECHANICAL SPECIFICATIONS FOR
SSOP ............................................................53
APPENDIX A: Device Nomenclature and
Ordering Information ..................................54
APPENDIX B: Additional Information ...............55
3


3Pages


DT28F016SA 電子部品, 半導体
28F016SA
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when writing several bytes in a row to the array or
erasing several blocks at the same time. The
28F016SA can also perform program operations to
one block of memory while performing erase of
another block.
The 28F016SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card information, ROM-executable
O/S or application code. Each block has an
associated nonvolatile lock-bit which determines the
lock status of the block. In addition, the 28F016SA
has a master Write Protect pin (WP#) which
prevents any modifications to memory blocks
whose lock-bits are set.
The 28F016SA contains three types of Status
Registers to accomplish various functions:
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory’s Status Register. This register, when
used alone, provides a straightforward upgrade
capability to the 28F016SA from a 28F008SA-
based design.
A Global Status Register (GSR) which informs
the system of Command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps for byte-wide and
word-wide modes are shown in Figures 5
and 6.
The 28F016SA incorporates an open drain RY/BY#
output pin. This feature allows the user to OR-tie
many RY/BY# pins together in a multiple memory
configuration such as a Resident Flash Array.
Other configurations of the RY/BY# pin are enabled
via special CUI commands and are described in
detail in the 16-Mbit Flash Product Family User’s
Manual.
The 28F016SA also incorporates a dual chip-enable
function with two input pins, CE0# and CE1#. These
pins have exactly the same functionality as the
regular chip-enable pin CE# on the 28F008SA. For
minimum chip designs, CE1# may be tied to ground
to use CE0# as the chip enable input. The
28F016SA uses the logical combination of these
6
two signals to enable or disable the entire chip. Both
CE0# and CE1# must be active low to enable the
device and, if either one becomes inactive, the chip
will be disabled. This feature, along with the open
drain RY/BY# pin, allows the system designer to
reduce the number of control pins used in a large
array of 16-Mbit devices.
The BYTE# pin allows either x8 or x16
read/programs to the 28F016SA. BYTE# at logic
low selects 8-bit mode with address A0 selecting
between low byte and high byte. On the other hand,
BYTE# at logic high enables 16-bit operation with
address A1 becoming the lowest order address and
address A0 is not used (don’t care). A device block
diagram is shown in Figure 1.
The 28F016SA is specified for a maximum access
time of 70 ns (tACC) at 5.0V operation (4.75V to
5.25V) over the commercial temperature range
(0°C to +70°C). A corresponding maximum access
time of 120 ns at 3.3V (3.0V to 3.6V and 0°C to
+70°C) is achieved for reduced power consumption
applications.
The 28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in the static
mode of operation (addresses not switching).
In APS mode, the typical ICC current is 1 mA at 5.0V
(0.8 mA at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 1.0 µA, typically, and
provides additional write protection by acting as a
device reset pin during power transitions. A reset
time is required from RP# switching high until
outputs are again valid. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
A CMOS standby mode of operation is enabled
when either CE0# or CE1# transitions high and RP#
stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
ICC standby current of 50 µA.
2.0 DEVICE PINOUT
The 28F016SA 56-lead TSOP Type I pinout
configuration is shown in Figure 2. The 56-lead
SSOP pinout configuration is shown in Figure 3.

6 Page



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部品番号部品説明メーカ
DT28F016SA

16-MBIT MEMORY

Intel
Intel
DT28F016SV

16-MBIT MEMORY

Intel
Intel


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