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PDF ISD5008 Data sheet ( Hoja de datos )
| Número de pieza | ISD5008 | |
| Descripción | VOICE RECORD/PLAYBACK DEVICE | |
| Fabricantes | nuvoton | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISD5008 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ISD5008
ISD5008
3V, SINGLE-CHIP
VOICE RECORD/PLAYBACK DEVICE
4- TO 8-MINUTES DURATION
Publication Release Date: Oct 31 2008
- 1 - Revision 1.2
1 page  
ISD5008
3 BLOCK DIAGRAM
MICROPHONE
MIC+
MIC -
AGCCAP
CAR KIT
AUX IN
XCLK
CHIP SET
ANA IN
6dB
MIC IN
AGC
1
(AGPD)
AUX IN
AUX IN
1
(INS0)
AMP
1
(AXPD)
( )AXG0
2 AXG1
FILTO
ANA IN
INP
SUM1 MUX
SUM1
Summing
AMP
SUM1
2
( S1M0 )
S1M1
ARRAY
1
(FLS0)
Low Pass
Filter
1
(FLPD)
FILTO
ANA IN
SUM2
Summing
AMP
2
( S2M0 )
S2M1
ARRAY
2
( S1S0)
S1S1
Internal
Clock
( )2 FLD0
FLD1
Multilevel
Storage Array
FTHRU
INP
FILTO
SUM1
VOL
SUM2
ANA
OUT
AMP
1
(AOPD)
( )3
AOS0
AOS1
AOS2
FILTO
VOL
AUX
OUT
AMP
ANA IN
AMP
1
(AIPD)
2
( AIG0 )
AIG1
Power Conditioning
SUM1
INP
ANA IN
SUM2
2
( VLS0)
VLS1
Volume
Control
( )3
VOL0
VOL1
VOL2
1
(VLPD)
SUM2
ANA IN
( )2
OPS0
OPS1
Spkr.
AMP
2
(OPA0)
OPA1
Device Control
CHIP SET
ANA OUT+
ANA OUT-
CAR KIT
AUX OUT
SPEAKER
SP+
SP-
VCCA VSSA VSSA VSSA VSSD VSSD VCCD VCCD
SCLK SS MOSI MISO INT RAC
Publication Release Date: Oct 31 2008
- 5 - Revision 1.2
5 Page 
ISD5008
6.1.5 Memory Architecture
The ISD5008 device contains a total of 1,920K Flash memory cells, which is organized as 1,200 rows
of 1,600 cells each. The duration is counted according to the number of rows, while the row number is
represented by the related 16 address bits of MOSI as described in the SPI section.
6.1.6 Programming
The ISD5008 device is also ideal for playback-only applications, where single- or multiple-message
playback is controlled through the SPI port. Once the desired message configuration is created,
duplicates can easily be generated via a third-party programmer. For more information on available
application tools and programmers, please see the Nuvoton website at www.Nuvoton-usa.com.
TABLE 2: EXTERNAL CLOCK INPUT
Duration Sample Rate
(Minutes)
(kHz)
Required Clock
(kHz)
4 8.0
1024
5 6.4
819.2
6 5.3
682.7
8 4.0
512
TABLE 3: INTERNAL SAMPLING RATE / FILTER EDGE
FLD1 FLD0 Sample
Rate (kHz)
Filter Pass Band
(kHz)
00
8
3.4
01
6.4
2.7
10
5.3
2.3
11
4
1.7
- 11 -
Publication Release Date: Oct 31 2008
Revision 1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISD5008.PDF ] | |
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