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PDF ISD5008 Data sheet ( Hoja de datos )
| Número de pieza | ISD5008 | |
| Descripción | Single-Chip Voice Record/Playback Device | |
| Fabricantes | ISD | |
| Logotipo |  |
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ISD5008
Single-Chip Voice Record/Playback Device
4-, 5-, 6-, and 8-Minute Durations
ISD5008 PRODUCT SUMMARY
Preliminary Datasheet
The ISD5008 ChipCorder product is a fully-inte-
grated, single-chip solution which provides seam-
less integration of enhanced voice record and
playback features for digital cellular phones (GSM,
CDMA, TDMA, PDC, and PHS), automotive com-
munications, GPS/navigation systems, and porta-
ble communication products. This low-power, 3-
volt product enables customers to quickly and
easily integrate 4 to 8 minutes of voice storage
features such as one-way and two-way (full du-
plex) call record, voice memo record, and call
screening/answering machine functionality.
Like other ChipCorder products, the ISD5008 inte-
grates the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array
on a single-chip. For enhanced voice features,
the ISD5008 eliminates external circuitry by also in-
tegrating automatic gain control (AGC), a power
amplifier/speaker driver, volume control, sum-
ming amplifiers, analog switches, and a car kit in-
terface. Input level adjustable amplifiers are also
included, providing a flexible interface for multiple
applications.
Figure: ISD5008 Block Diagram
MICROPHONE
MIC+
MIC -
AGCCAP
CAR KIT
AUX IN
XCLK
CHIP SET
ANA IN
6dB
MIC IN
AGC
1
(AGPD)
AUX IN
AUX IN
1
(INS0)
AMP 1
(AXPD)
( )AXG0
2 AXG1
FILTO
ANA IN
INP
SUM1 MUX
SUM1
Summing
Σ AMP
SUM1
2
( )S1M0
S1M1
ARRAY
1
(FLS0)
Low Pass
Filter
1
(FLPD)
FILTO
ANA IN
SUM2
Summing
Σ AMP
2
( )S2M0
S2M1
ARRAY
2
( )S1S0
S1S1
Internal
Clock
( )2 FLD0
FLD1
Multilevel
Storage Array
FTHRU
INP
FILTO
SUM1
VOL
SUM2
ANA
OUT
AMP
1
(AOPD)
3
( )AOS0
AOS1
AOS2
FILTO
VOL
AUX
OUT
AMP
ANA IN
AMP
1
(AIPD)
2
( )AIG0
AIG1
Power Conditioning
SUM1
INP
ANA IN
SUM2
2
( )VLS0
VLS1
Volume
Control
3
( )VOL0
VOL1
VOL2
1
(VLPD)
SUM2
ANA IN
2
( )OPS0
OPS1
Spkr.
AMP
2
( )OPA0
OPA1
Device Control
CHIP SET
ANA OUT+
ANA OUT-
CAR KIT
AUX OUT
SPEAKER
SP+
SP-
VCCA VSSA VSSA VSSA VSSD VSSD VCCD VCCD
SCLK SS MOSI MISO INT RAC
August 2000
ISD · 2727 North First Street, San Jose, CA 95134 · TEL: 408/943-6666 · FAX: 408/544-1787 · http://www.isd.com
1 page  
ISD5008 Product
2 PIN DESCRIPTIONS
2.1 DIGITAL I/O PINS
SCLK
(Serial Clock)
The SCLK is the clock input to the ISD5008. Gener-
ated by the master microcontroller, the SCLK syn-
chronizes data transfers in and out of the device
through the MISO and MOSI lines. Data is latched
into the ISD5008 on the rising edge of SCLK and
shifted out on the falling edge.
SS (Slave Select)
This input, when LOW, will select the ISD5008 de-
vice.
MOSI
(Master Out Slave In)
MOSI is the serial data input to the ISD5008 de-
vice. The master microcontroller places data to
be clocked into the ISD5008 device on the MOSI
line one-half cycle before the rising edge of SCLK.
Data is clocked into the device LSB (Least Signifi-
cant Bit) first.
OVF Flag. The overflow flag indicates that the end
of the ISD5008’s analog memory has been
reached during a record or playback operation.
EOM Flag. The end of message flag is set only
during playback, when an EOM is found. There are
eight possible EOM markers per row.
RAC
(Row Address Clock)
RAC is an open drain output pin that marks the
end of a row. At the 8 kHz sample frequency, the
duration of this period is 200 ms. There are 1,200
rows of memory in the ISD5008 devices. RAC stays
HIGH for 175 ms and stays LOW for the remaining
25 ms before it reaches the end of the row.
The RAC pin remains HIGH for 109.38 µsec and
stays LOW for 15.63 µsec under the Message Cue-
ing mode. See Table 15 Timing Parameters for
RAC timing information at other sample rates.
When a record command is first initiated, the RAC
pin remains HIGH for an extra TRACLO period, to
load sample and hold circuits internal to the de-
vice. The RAC pin can be used for message man-
agement techniques.
MISO
(Master In Slave Out)
MISO is the serial data output of the ISD5008 de-
vice. Data is clocked out on the falling edge of
SCLK. This output goes into a high-impedance
state when the device is not selected. Data is
clocked out of the device LSB first.
INT (Interrupt)
INT is an open drain output pin. The ISD5008 inter-
rupt pin goes LOW and stays LOW when an Over-
flow (OVF) or End of Message (EOM) marker is
detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the mes-
sage cueing cycles. The interrupt is cleared the
next time an SPI cycle is completed. The interrupt
status can be read by a RINT instruction that will
give one of the two flags out the MISO line.
XCLK
(External Clock Input)
The external clock input for the ISD5008 product
has an internal pull-down device. Normally, the
ISD5008 is operated at one of four internal rates
selected for its internal oscillator by the Sample
Rate Select bits. If greater precision is required, the
device can be clocked through the XCLK pin as
described in Table 2.
Because the antialiasing and smoothing filters
track the Sample Rate Select bits, one must, for
optimum performance, change the external
clock AND the Sample Rate Configuration bits to
one of the four values to properly set the filters to
the correct cutoff frequency as described in Table
3. The duty cycle on the input clock is not critical,
as the clock is immediately divided by two inter-
nally. If the XCLK is not used, this input should be
connected to VSSD.
2 Voice Solutions in Silicon™
5 Page 
ISD5008 Product
Figure 6: AUX IN and ANA IN
Chip Set
Car Kit AUX IN
AUX IN
AMP
AUX IN AMP
1 (AXPD)
2 (AXG1, AXG0)
AXPD
0 Power Up
1 Power Down
ANA IN
ANA IN
AMP
AXG1
0
0
1
1
AXG0
0
1
0
1
Input Gain 0TLP Input Level
1 .694
1.414
.491
2 .347
2.828
.245
ANA IN AMP
1 (AIPD)
2 (AIG1,AIG0)
AIPD
0
1
Power Up
Power Down
AIG1
0
0
1
1
AIG0
0
1
0
1
Input Gain 0TLP Input Level
0.625
1.11
0.883
.785
1.250
.555
1.767
.393
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
8 Voice Solutions in Silicon™
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISD5008.PDF ] | |
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