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PDF ISD9130 Data sheet ( Hoja de datos )
| Número de pieza | ISD9130 | |
| Descripción | 32-Mbit Microcontrolle | |
| Fabricantes | nuvoton | |
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ISD9100 Series Datasheet
ISD Cortex™-M0 ChipCorder
ISD9100 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ChipCorder microcontroller
based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: January 8, 2016
- 1 - Revision V1.41
1 page  
ISD9100 Series Datasheet
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Differential Audio PWM Output (DPWM)
– Direct connection of speaker
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Timers
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from micro seconds to seconds (depending on clock source)
– WDT can wake up power down/sleep.
– Interrupt or reset selectable on watchdog time-out.
RTC
– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
– Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR)
PWM/Capture
– Built-in up to two 16-bit PWM generators provide two PWM outputs or one complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt
UART
– UART ports with flow control (TX, RX, CTS and RTS)
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function
– Programmable baud-rate generator up to 1/16 of system clock.
SPI
– Master up to 20 Mbps / Slave up to 10 Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 32 bits
– MSB or LSB first data transfer
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support for burst transfers.
I2C
– Master/Slave up to 1Mbit/s
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master).
-5-
Release Date: January 8, 2016
Revision V1.41
5 Page 
ISD9100 Series Datasheet
Pin No.
LQFP QFN Pin Name
48 33
I2S_SDI
PA.5
28 -
I2S_BCLK
PA.4
29 -
I2S_FS
PA.3
30 19 SPI_MISO0
I2C_SDA
PA.2
31 20
SPI_SSB0
32 21 VDD33
PA.1
33 22 SPI_SCLK
I2C_SCL
PA.0
34 23 SPI_MOSI0
MCLK
35 24 VCCLDO
PA.14
36 - SDCLK
SDCLKn
PA.13
PWM1
37 -
SPKM
I2S_BCLK
PA.12
PWM0
38 -
SPKP
I2S_FS
39 25 XO32K
40 26 XI32K
Pin Type
Alt
CFG
Description
I 1 Serial Data In for I2S interface
I/O 0 General purpose input/output pin; Port A, bit 5
I/O 1 Bit Clock for I2S interface
I/O 0 General purpose input/output pin; Port A, bit 4
I/O 1 Frame Sync Clock for I2S interface
I/O 0 General purpose input/output pin; Port A, bit 3
I 1 Master In, Slave Out channel 0 for SPI interface
I/O 2 Serial Data, I2C interface
I/O 0 General purpose input/output pin; Port A, bit 2
I/O 1 Slave Select Bar 0 for SPI interface
P
LDO Regulator Output. If used, a 1µF capacitor must be
placed to ground. If not used then tie to VCCD.
I/O 0 General purpose input/output pin; Port A, bit 1
I/O 1 Serial Clock for SPI interface
I/O 2 Serial Clock, I2C interface
I/O 0 General purpose input/output pin; Port A, bit 2
O 1 Master Out, Slave In channel 0 for SPI interface
O 2 Master clock output.
P Power Supply for LDO, should be connected to VCCD
I/O 0 General purpose input/output pin; Port A, bit 14
O 1 Clock output for digital microphone mode.
O 2 Inverse Clock output for digital microphone mode.
I/O 0 General purpose input/output pin; Port A, bit 13
O 1 PWM1 Output.
O 2 Equivalent to SPK-.
I/O 3 Bit Clock for I2S interface
I/O 0 General purpose input/output pin; Port A, bit 12
O 1 PWM0 Output.
O 2 Equivalent to SPK+
I/O 3 Frame Sync Clock for I2S interface
O 32.768kHz Crystal Oscillator Output
I 32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
- 11 -
Release Date: January 8, 2016
Revision V1.41
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ISD9130.PDF ] | |
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