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PDF ISD9331 Data sheet ( Hoja de datos )
| Número de pieza | ISD9331 | |
| Descripción | 32-Mbit Microcontrolle | |
| Fabricantes | nuvoton | |
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ISD9300 Series Datasheet
ISD Cortex™-M0 ChipCorder
ISD9300 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ChipCorder microcontroller
based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: Mar 17, 2016
- 1 - Revision V1.12
1 page  
ISD9300 Series Datasheet
– Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
– Boost gain stage of 26dB, giving maximum total gain of 61dB.
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Differential Audio PWM Output (DPWM)
– Direct connection of speaker
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Timers
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from micro seconds to seconds (depending on clock source)
– WDT can wake up sleep.
– Interrupt or reset selectable on watchdog time-out.
RTC
– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
– Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR)
PWM/Capture
– Six 16-bit PWM generators provide six single ended PWM outputs or three complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt
UART
– UART ports with flow control (TX, RX, CTS and RTS)
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function
– Programmable baud-rate generator up to 1/16 of system clock.
SPI
– SPI clock up to 24MHz.
– SPI data rate in Quad mode up to 98Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 4 bytes.
– MSB or LSB first data transfer
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support for burst transfers.
– Dual/Quad SPI support.
Release Date: Mar 17, 2016
- 5 - Revision V1.12
5 Page 
ISD9300 Series Datasheet
Pin No.
LQFP
64
Pin Name
SPI_SSB1
PA.4
40
I2S_FS
PB.13
SPI_MOSI1
41
PWM5
PWM4B
PA.3
42 SPI_MISO0
I2C_SDA
PA.2
43
SPI_SSB0
44 VDD33
PB.12
SPI_MISO1
45
PWM4
PWM5B
PA.1
46 SPI_SCLK
I2C_SCL
PA.0
47 SPI_MOSI0
MCLK
48 VCCLDO
PA.14
TM0
49
SDCLK
PWM4
PA.13
50 PWM1
SPKM
Pin Type
Alt
CFG
Description
O 3 SPI Slave Select 1
I/O 0 General purpose input/output pin; Port A, bit 4
I/O 1 I2S Frame Sync
I/O 0 General purpose input/output pin; Port B, bit 13.
O 1 SPI Channel 1 Master Out, Slave In
O 2 PWM5 Output
O 3 PWM Channel 4 Complementary Output
I/O 0 General purpose input/output pin; Port A, bit 3
I 1 SPI Channel 0 Master In, Slave Out
I/O 2 I2C Serial Data
I/O 0 General purpose input/output pin; Port A, bit 2
I/O 1 SPI Slave Select 0
P
LDO Regulator Output. If used, a 1µF capacitor must be placed
to ground. If not used then tie to VCCD.
I/O 0 General purpose input/output pin; Port B, bit 13.
O 1 Master In, Slave Out channel 1 for SPI interface
O 2 PWM4 Output
O 3 PWM channel 5 Complementary Output
I/O 0 General purpose input/output pin; Port A, bit 1
I/O 1 SPI Serial Clock
I/O 2 I2C Serial Clock
I/O 0 General purpose input/output pin; Port A, bit 2
O 1 SPI Channel 0 Master Out, Slave In
O 2 Master clock output.
P Power Supply for LDO, should be connected to VCCD
I/O 0 General purpose input/output pin; Port A, bit 14
I 1 External input to Timer 0
O 2 Inverse Clock output for digital microphone mode.
O 3 PWM4 Output
I/O 0 General purpose input/output pin; Port A, bit 13
O 1 PWM1 Output.
O 2 Equivalent to SPK-.
- 11 -
Release Date: Mar 17, 2016
Revision V1.12
11 Page | ||
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