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PDF LT4294 Data sheet ( Hoja de datos )
| Número de pieza | LT4294 | |
| Descripción | IEEE 802.3bt PD Interface Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT4294
IEEE 802.3bt
PD Interface Controller
FEATURES
nn IEEE 802.3af/at/bt (Draft 2.3) Powered Device (PD)
Controller
nn Supports Up to 71W PDs
nn 5-Event Classification Sensing
nn Superior Surge Protection (100V Absolute Maximum)
nn Wide Junction Temperature Range (–40°C to 125°C)
nn Overtemperature Protection
nn Integrated Signature Resistor
nn External Hot Swap N-Channel MOSFET for Lowest
Power Dissipation and Highest System Efficiency
nn Configurable Aux Power Support as Low as 9V
nn Easy Migration Between LTPoE++® PDs and IEEE
802.3bt PDs
nn Pin Compatible with LT4275A/B/C
nn Available in 10-Lead MSOP and 3mm × 3mm DFN
Packages
APPLICATIONS
nn High Power Wireless Data Systems
nn Outdoor Security Camera Equipment
nn Commercial and Public Information Displays
nn High Temperature Industrial Applications
DESCRIPTION
The LT®4294 is an IEEE 802.3af/at/bt (Draft 2.3)-compliant
powered device (PD) interface controller. The T2P output
indicates the number of classification events received
during IEEE 802.3bt-compliant mutual identification and
negotiation of available power.
The LT4294 utilizes an external, low RDS(ON) N-channel
hot swap MOSFET and supports the LT4320/LT4321 ideal
diode bridges, to extend the end-to-end power delivery
efficiency and eliminate costly heat sinks. The LT4294
also includes a power good output, onboard signature
resistor, undervoltage lockout, and thermal protection.
Start-up inrush current is adjustable with an external
capacitor. Auxiliary power override is supported as low
as 9V with the AUX pin.
The LT4294 can be configured to support all possible
802.3bt, 802.3at and 802.3af power levels with external
component changes. Pin-for-pin compatibility with the
LT4275 family of PD Interface Controllers enables easy
migration between LTPoE++ PDs and IEEE 802.3bt-
compliant PDs.
L, LT, LTC, LTM, Linear Technology and the Linear logo and LTPoE++, are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
IEEE 802.3bt Single-Signature Powered Device Interface
VAUX (9V TO 60V)
~
DATA
PAIR ~
SPARE
PAIR
~
~
+
VPORT
–
+
–
CPD
0.1µF
RCLS
PSMN040-100MSE
3.3k
VPORT HSGATE
AUX
RCLS++
RCLASS
RCLASS++
LT4294
GND
+
47nF
HSSRC
PWRGD
T2P
4294 TA01a
CPORT
VIN
ISOLATED
POWER
SUPPLY
RUN
+
VOUT
–
OPTO
PSE TYPE
(TO µP)
For more information www.linear.com/LT4294
Single-Signature
Power Classification
AVAILABLE
POWER
CLASS AT PD INPUT
0 13W
1 3.84W
2 6.49W
3 13W
4 25.5W
5 40W
6 51W
7 62W
8 71W
4294f
1
1 page  
LT4294
PIN FUNCTIONS
GND (Pins 1, 5, DFN Exposed Pad Pin 11): Device Ground.
Exposed Pad must be electrically and thermally connected
to pin 5 and PCB GND.
AUX (Pin 2): Auxiliary Sense. A resistive divider from the
auxiliary power input to AUX sets the voltage at which the
auxiliary supply takes over. In auxiliary power operation,
HSGATE pulls down, the signature resistor disconnects,
classification is disabled, the PWRGD pin is high imped-
ance and T2P indicates max available power. The AUX pin
sinks IAUXH when below its threshold voltage of VAUXT to
provide hysteresis. Connect to GND when not used.
RCLASS (Pin 3): Configurable PoE Classification Resistor.
See Table 2.
RCLASS++ (Pin 4): Configurable PoE Classification Resis-
tor. See Table 2.
T2P (Pin 6): PSE Type Indicator, Open-Drain Output. See
the Applications Information section for pin behavior.
PWRGD (Pin 7): Power Good Indicator, Open-Drain Output.
Pulls to GND during VCLASS and inrush.
HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-
nect to source of the external MOSFET.
HSGATE (Pin 9): External Hot Swap MOSFET Gate Control,
Output. Connect to gate of the external MOSFET.
VPORT (Pin 10): PD interface upper power rail and external
Hot Swap MOSFET drain connection.
BLOCK DIAGRAM
VPORT
VPORT
VOLTAGE AND
CURRENT REFERENCES
PWRGD
AUX +
~6.5V 6.3V –
1.4V
RCLASS
+
– EN
VPORT
CONTROL
LOGIC
ON
CHARGE
PUMP
HSGATE
VGOC HSSRC
OVERTEMP
CLASSIFICATION
LOGIC
GND
T2P
VPORT
+ 1.4V
EN –
RCLASS++
4294 BD
For more information www.linear.com/LT4294
4294f
5
5 Page 
APPLICATIONS INFORMATION
For PD applications that require an auxiliary power input,
install a TVS between VIN and GND as close as possible
to the LT4294. For extremely high cable discharge and
surge protection, contact Linear Technology Applications.
Exposed Pad
The LT4294 DFN package has an exposed pad that is
internally electrically connected to GND. The exposed pad
may only be connected to GND on the printed circuit board.
LT4294
LAYOUT CONSIDERATIONS
Avoid excessive parasitic capacitance on the RCLASS
and RCLASS++ pins and place resistors RCLS and RCLS++
close to the LT4294.
It is strictly required for maximum protection to place the
0.1μF input capacitor, CPD, and transient voltage suppres-
sor as close to the LT4294 as possible. When operating
the LT4294 with the LT4321, place a 0.047μF capacitor,
CPD1, as close as possible to the LT4294 VPORT and GND
pins (pin 10 and pin 5, respectively), and a 0.047μF ca-
pacitor, CPD2, as close as possible to the LT4321 OUTP
and OUTN pins.
TYPICAL APPLICATIONS
1
DATA
PAIRS
2
3
6
4
SPARE
PAIRS
5
7
High Efficiency 25.5W PD Solution with 12VDC and 24VAC Auxiliary Input
PSMN075-100MSE ×4
VAUX
9V TO 57VDC
OR 24VAC
MMSD4148
×3
BSZ110N06NS3 ×4
TG2
TG1
OUTP
LT4320
IN1
IN2
BG2
BG1
OUTN
PSMN075-100MSE
1µF
TG12 BG12
IN12
BG36 TG36
OUTP
EN
IN36 LT4321
IN45
EN
IN78 OUTN
CPD1
0.047µF
VPORT
HSGATE
HSSRC
SMAJ58A
CPD2
0.047µF
158k
0.1µF
AUX
931k
PWRGD
LT4294 RCLASS
GND
4294 TA03
+
3.3k
34.8Ω
150nF
680µF
VIN
100k
ISOLATED
POWER
SUPPLY
RUN
GND
+
–VOUT
BG78 TG78
TG45 BG45
8
WURTH 749022017
PSMN075-100MSE ×4
For more information www.linear.com/LT4294
4294f
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11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LT4294.PDF ] | |
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