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MPC9774 の電気的特性と機能

MPC9774のメーカーはMotorola Semiconductorsです、この部品の機能は「LVCMOS PLL CLOCK GENERATOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 MPC9774
部品説明 LVCMOS PLL CLOCK GENERATOR
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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MPC9774 Datasheet, MPC9774 PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9774/D
Rev 1, 04/2002
Product Preview
3.3V/2.5V 1:14 LVCMOS PLL
Clock Generator
The MPC9774 is a 3.3V or 2.5V compatible, 1:14 PLL based clock
generator targeted for high performance low-skew clock distribution in
mid-range to high-performance networking, computing and telecom
applications. With output frequencies up to 125 MHz and output skews
less than 300 ps1 the device meets the needs of the most demanding
clock applications.
Features
1:14 PLL based low-voltage clock generator
2.5V or 3.3V power supply
Internal power–on reset
Generates clock signals up to 125 MHz
Maximum output skew of 300 ps1
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +85°C
Pin and function compatible to the MPC974
MPC9774
3.3V/2.5V 1:14 LVCMOS
PLL CLOCK GENERATOR
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
Functional Description
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range.
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The
VCO_SEL pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC9774 has an internal power–on reset.
The MPC9774 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)
accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP
package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2002
1

1 Page





MPC9774 pdf, ピン配列
MPC9774
Table 1. PIN CONFIGURATION
Pin I/O Type
CCLK0
Input LVCMOS
CCLK1
Input LVCMOS
FB_IN
Input LVCMOS
CCLK_SEL
Input LVCMOS
VCO_SEL
Input LVCMOS
PLL_EN
Input LVCMOS
MR/OE
Input LVCMOS
CLK_STOP
Input LVCMOS
FSEL_A
Input LVCMOS
FSEL_B
Input LVCMOS
FSEL_C
Input LVCMOS
FSEL_FB[1:0] Input LVCMOS
QA[4:0]
Output LVCMOS
QB[4:0]
Output LVCMOS
QC[3:0]
Output LVCMOS
QFB
Output LVCMOS
GND
Supply Ground
VCC_PLL
Supply VCC
VCC
Supply VCC
Function
PLL reference clock
Alternative PLL reference clock
PLL feedback signal input, connect to QFB
LVCMOS clock reference select
VCO operating frequency select
PLL enable/PLL bypass mode select
Output enable/disable (high-impedance tristate) and device reset
Output enable/clock stop (logic low state)
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock outputs (Bank A)
Clock outputs (Bank B)
Clock outputs (Bank C)
PLL feedback output. Connect to FB_IN.
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. Function Table (MPC9774 configuration controls)
Control Default
0
CCLK_SEL 0 Selects CCLK0 as PLL refererence signal input
VCO_SEL
0 Selects VCO ÷ 2. The VCO frequency is scaled by a
factor of 2 (high input frequency range)
1
Selects CCKL1 as PLL reference signal input
Selects VCO ÷ 4. The VCO frequency is scaled by a
factor of 4 (low input frequency range).
PLL_EN
1 Test mode with the PLL bypassed. The reference clock is Normal operation mode with PLL enabled.
substituted for the internal VCO output. MPC9774 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
CLK_STOP 1 QA, QB an QC outputs disabled in logic low state. QFB Outputs enabled (active)
is not affected by CLK_STOP. CLK_STOP deassertion
may cause the initial output clock pulse to be distorted.
MR/OE
1 Outputs disabled (high-impedance state) and reset of the Outputs enabled (active)
device. During reset/output disable the PLL feedback
loop is open and the internal VCO is tied to its lowest
frequency. The MPC9774 requires reset after any loss of
PLL lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than one reference clock cycle
(CCLKx). The device is reset by the internal power–on
reset (POR) circuitry during power–up.
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
See Table 3 and Table 4 for the device frequency configuration.
TIMING SOLUTIONS
3
MOTOROLA


3Pages


MPC9774 電子部品, 半導体
MPC9774
Table 8. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 85°C)a b
Symbol
Characteristics
Min
fref Input reference frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
25.0
16.6
12.5
8.33
6.25
4.16
Typ Max Unit Condition
62.5
41.6
31.25
20.83
15.625
10.41
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fVCO
fMAX
Input reference frequency in PLL bypass modec
VCO frequency ranged
Output Frequency
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
200
50.0
25.0
16.6
12.5
8.33
TBD
500
125.0
62.5
41.6
31.25
20.83
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL bypass
PLL locked
frefDC
tr, tf
Reference Input Duty Cycle
CCLKx Input Rise/Fall Time
40 60 %
1.0 ns 0.8 to 2.0V
t() Propagation Delay (static phase offset)
CCLKx or FB_IN
±150
ps PLL locked
tsk(O)
DC
Output-to-output Skewe
Output duty cycle
300 ps
45 50 55 %
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT()
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthg
0.1
RMS (1 σ)f
RMS (1 σ)
RMS (1 σ)
TBD
TBD
TBD
1.0 ns 0.55 to 2.4V
8 ns
8 ns
ps
ps
ps
kHz
tLOCK
Maximum PLL Lock Time
10 ms
a All AC characteristics are design targets and subject to change upon device characterization.
b AC characteristics apply for parallel output termination of 50to VTT.
c In bypass mode, the MPC9774 divides the input reference clock.
d The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M VCO_SEL).
e See application section for part-to-part skew calculation.
f See application section for a jitter calculation for other confidence factors than 1 σ.
g -3 dB point of PLL transfer characteristics.
MOTOROLA
6 TIMING SOLUTIONS

6 Page



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共有リンク

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