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L24C256 の電気的特性と機能

L24C256のメーカーはLIZEです、この部品の機能は「EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 L24C256
部品説明 EEPROM
メーカ LIZE
ロゴ LIZE ロゴ 




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L24C256 Datasheet, L24C256 PDF,ピン配置, 機能
Shenzhen LIZE Electronic Technology Co., Ltd
SPECIFICATION
L24C128/L24C256/L24C512
Version 1.1
Features
reservesthe rightto changethis documentationwithout priornotice.

1 Page





L24C256 pdf, ピン配列
Tel:86-755-8835 3502/03/04
Fax:86-755-8835 3509
Website:http://www.lizhiic.com
___________________________________________________________________________________
Pin Descriptions
Pin
number
Designation
1–2
A0 – A1
5 SDA
6 SCL
7 WP
Type
I
I/O
&
Open-drain
I
I
Name and Functions
Address Inputs
DEVICE/PAGE ADDRESSES (A1, A0):
The A1 and A0 pins are device address
inputs that are hardwired or left not
connected for hardware compatibility with
other 24Cxx devices. When the pins are
hardwired, as many as four 128K/256K
devices may be addressed on a single bus
system (device addressing is discussed in
detail under the Device Addressing
section). If the pins are left floating, the
A2, A1 and A0 pins will be internally pulled
down to GND if the capacitive coupling to
the circuit board VCC plane is <3 pF. If
coupling is >3 pF, recommends connecting
the address pins to GND.
Serial Data
SERIAL DATA (SDA): The SDA pin is
bi-directional for serial data transfer. This
pin is open-drain driven and may be
wire-ORed with any number of other
open-drain or open- collector devices.
Serial Clock Input
SERIAL CLOCK (SCL): The SCL input is
used to positive edge clock data into each
EEPROM device and negative edge clock
data out of each device.
Write Protect
WRITE PROTECT (WP): The write
protect input, when connected to GND,
allows normal write operations. When WP
is connected high to VCC, all write
operations to the memory are inhibited. If
the pin is left floating, the WP pin will be
internally pulled down to GND if the
capacitive coupling to the circuit board VCC
plane is <3 pF. If coupling is >3 pF,
recommends connecting the pin to GND.
Switching WP to VCC prior to a write
operation creates a software write protect
function. The write protection feature is
enabled and operates as shown in the
following Table 1.
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 1.1
Date: 16, Nov. 2013
Page: 3 of 15


3Pages


L24C256 電子部品, 半導体
Tel:86-755-3680 0780
Website:http://www.lizhiic.com
Fax:86-755-8835 3509
________________________________________________________________________________________________
hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that
biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the
chip will return to a standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins
prevent small noise spikes from activating the device.
DATA SECURITY: The L24C128/L24C256 has a hardware data protection scheme
that allows the user to write protect the entire memory when the WP pin is at VCC.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address
word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0”
and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will
output a “0” and the addressing device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR,
to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (see Figure 5 on page 8).
PAGE WRITE: The 128K/256K devices are capable of 64-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of
the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will
respond with a “0” after each data word received. The microcontroller must terminate the page
write sequence with a stop condition (see Figure 6 on page 8).
The data word address lower six (128K/256K) bits are internally incremented following the receipt
of each data word. The higher data word address bits are not incremented, retaining the memory
page row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and
the EEPROM inputs are disabled, acknowledge polling can be initiated. This
involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write
cycle has completed will the EEPROM respond with a “0”, allowing the read or write
sequence to continue.
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address
accessed during the last read or write operation, incremented by one. This address stays valid
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 1.1
Date: 16, Nov. 2013
Page: 6 of 15

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部品番号部品説明メーカ
L24C256

EEPROM

LIZE
LIZE


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