6526 Datasheet PDF - Commodore
| Part Number | 6526 | |
| Description | COMPLEX INTERFACE ADAPTER | |
| Manufacturers | Commodore | |
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, . . , commodore
~ aanlcanduct;ar group
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MPS
6526
COMPLEX
INTERFACE
ADAPTER
(CIA)
6526 COMPLEX INTERFACE ADAPTER (CIA)
DESCRIPTION
The 6526 Complex Interface Adapter (CIA) is a 65XX bus compatible peripheral Interface device
with extremely flexible timing and I/O capabilities.
FEATURES
• 16 Individually programmable I/O lines
• 8 or 16-Bit handshaking on read or write
• 2 independent, linkable 16-Bit interval timers
• 24-hour (AM/PM) time of day clock with programmable alarm
• 8-Bit shift register for serial I/O
• 2TTL Load capability
• CMOS compatible I/O lines
• 1 or 2 MHz operation available
ORDERING INFORMATION
MXS 6526
1 40 CNT
PAO 2
39 SP
PA1 3
PA2 4
PA3 5
PA4 6
PA5 7
38 RSO
37 RS1
36 RS2
35 RS3
34 RES
PA6 8
33 DBO
PA7 9
32 DB1
PBO 10 6526 31 DB2
PB1 11
30 DB3
PB2 12
29 DB4
PB3 13
28 DB5
PB4 14
27 DB6
PB5 15-
PB6 16
PB7 17
Pc 18
TOO 19
vee 20
26 DB7
25 ~2
24 FLAG
23 es
22 RNV
21 IRQ
2-84
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MPS
6526
Symbol
TCYC
TA,TF
TCHW
TCLW
TpD
TWCS
TAOS
TADH
TAWS
TAWH
TDS
TDH
TpS
TWCS(2)
TADS
TADH
TAWS
TAWH
TACC
TCO(3)
TOR
6626 TIMING CHARACTERISTICS
Ch....ct.rlltlc
~2Clock
Cycle Time
Aise and Fall Time
Clock Pulse Width (High)
Clock Pulse Width (Low)
Write Cycle
Qytput Delay From 112
CS low while 112 high
Address Setup Time
Address Hold Time
ANI Setup Time
ANI Hold Time
Data Bus Setup Time
Data Bus Hold Time
Read Cycle
Port Setup Time
CS low while %2 high
Address Setup Time
Address Hold Time
ANI Setup Time
RNI Hold Time
Data Access from RS3-RSO
Data Access from GS
Data Release Time
MIN
1M"z
MAX
1,000
420
420
20,000
25
10,000
10,000
1,000
420
0
10
0
0
150
0
300
420
0
10
0
0
550
320
50
MIN
500
200
200
200
0
5
0
0
75
0
150
200
0
5
0
0
25
2M Hz
MAX
20,000
25
10,000
10,000
500
275
150
NOTES: 1 - All timings are referenced from VIL max and VI'eSin on inputs and VOL max and VOH min on outputs.
2 - TWGS is measured from the I~ter of 1'2 high or low. CS must be low at least until the end of 1'2 high.
3 - TCO is measured from the later of 112 high or CS low.
Valid data is available only after the later of TACG or TCO.
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
REGISTER MAP
1183 R82 AS1 RIO REG
0 0 0 0 0 PRA
PERIPHERAL DATA REG A
0001
PRB
PERIPHERAL DATA REG B
00
0
DORA
DATA DIRECTION REG A
00 11
DDRB
DATA DIRECTION REG B
0
00
TA LO
TIMER A LOW REGISTER
0
01
TA HI
TIMER A HIGH REGISTER
0
0
TB LO
TIMER B LOW REGISTER
0 1 1 1 7 TB HI
TIMER B HIGH REGISTER
0 0 0 8 TOO 10THS 10THS OF SECONDS REGISTER
0 0 1 9 TOO SEC SECONDS REGISTER
0 0 A TOO MIN MINUTES REGISTER
0 1 1 B TOO HR HOURS - AM/PM REGISTER
0 0 C SDR
SERIAL DATA REGISTER
0 0 ICR INTERRUPT CONTROL REGISTER
0 E CRA
CONTROL REG A
F CRB
CONTROL REG B
6626 FUNCTIONAL DESCRIPTION
I/O Ports (PRA, PRB, DORA, DDRB)
Ports A and B each consist of an 8-bit Peripheral
Data Register (PR) and an 8-bit Data Direction Register
(DDR).lf a bit in the DDR is set to a one, the correspond-
ing bitin the PR is an output, if a DDA bit is set to a zero,
the corresponding PR bit is defined as an input. On a
READ, the PR reflects the information present on the
actual port pins (PAO-PA7, PBo-PB7) for both input and
output bits. Port A and Port B have passive pull-up
devices as well as active pull-ups, providing both
CMOS and TTL compatibility. Both ports have two TTL
load drive capability. In addition to normal I/O opera-
tion, PB6 and PB7 also provide timer output functions.
2-88
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 6526 electronic component. |
| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 6526.PDF Datasheet ] | |
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