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6525 の電気的特性と機能

6525のメーカーはCommodoreです、この部品の機能は「TRI-PORT INTERFACE」です。


製品の詳細 ( Datasheet PDF )

部品番号 6525
部品説明 TRI-PORT INTERFACE
メーカ Commodore
ロゴ Commodore ロゴ 




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6525 Datasheet, 6525 PDF,ピン配置, 機能
v -'-'commodore
aamicanduct;or group
~~@@
6525 TRI·PORT INTERFACE
MPS
6525
TRI-PORT
INTERFACE
CONCEPT ...
The 6525 TRI·PORT Interface (TPI) is designed to simplify the implementation of complex I/O
operations in microcomputer systems. It combines two dedicated a·bit 110 ports with a third a-bit port
programmable for either normal 110 operation or priority interrupt/handshaking control. Depending on
the mode selected, the 6525 can provide 24 individually programmable 110 lines or 16 110 lines, 2
handshake lines and 5 priority interrupt inputs.
FEATURES:
• 24 individually programmable 110 lines or
16 110 lines, 2 handshake lines and 5 in-
terrupt inputs.
• Priority or non-priority interrupts
• Automatic handshaking
• Completely static operation
• Two TTL Drive Capabi Iity
• a directly addressable registers
• 1 MHz, 2MHz and 3MHz operation
6525 REGISTERS
·000
001
010
011
100
101
110
111
RO PRA - Port Register A
R1 PRB - Port Register B
R2 PRC - Port Register C
R3 DDRA - Data Qirection Register A
R4 DDRB - Data Direction Register B
R5 DDRC - Data Qirection Register C
R6 CR-Control Register
R7 AIR-Active Interrupt Register
-NOTE: RS2. RS1, RSO respectively
ORDER NUMBER:
MXSM25
T
L SPEED RANGE
=NO SUFFIX 450 ns
A=225 ns
B = 155 ns
PACKAGE DESIGNATOR
C=CERAMIC
P=PLASTIC
2-76
6525 PIN CONFIGURATION
Vss
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
cs
R/W
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 DB7
39 DBB
38 DB5
37 DB4
36 DB3
35 DB2
34 DB1
33 DBO
32 PC7
31 PC6
30 PC5
29 PC4
26 PC3
27 PC2
26 PC1
25, pco
24 RSO
23 RS1
22' RS2
21 REs

1 Page





6525 pdf, ピン配列
MPS
6525
MAXIMUM RATINGS
Supply Voltage, Vcc
InpuVOutput Voltage, VI N
Operating Temperature, TOp
Storage Temperature, TSTG
-O.3V to +7.OV
-O.3V to +7.OV
O°Cto 70°C
-55°C to 150°C
All inputs contain protection Circuitry to prevent damage
due to high static discharges. Care should be exer-
cised to prevent unnecessary application of voltages in
excess of the allowable limits.
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specifica-
tion is not implied and exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
CHARACTERISTICS (VCC = 5.0 V ± 5%, VSS = OV, TA = to 70°C)
CHARACTERISTIC
SYMBOL
MIN
TYP
Input High Voltage (Normal Operating Levels)
VIH
+ 2.0
1.5
Input Low Voltage (Normal Operating Levels)
Input Leakage Current
Vin = 0 to 5.0 V_
WRITE, RES, CS, RS2-RSO
VIL
liN
-0.3
0
1.2
±1.D
Three-State (Off, State) Input Current
(Vin = 0.4 to 2.4 V VCC= max)
00-07, PAO-P7, PBO-PB7, PCG-PC?
ITSI 0 ± 2.0
Output High Voltage
(VCC = min, Load = 200 IJA)
VOH
2.4
3.5
Output Low Voltage
(VCC = min, Load = 3.2 mAl
VOL
VSS
0.2
Output High Current (Sourcing)
(VOH = 2.4 V)
Output Low Current (Sinking)
(VOL = 0.4 V)
Supply Current
Input Capacitance
(Vin OV, TA = 25°C, f = 1.0 MHz)
00-07, PAG-PA7, PBO-PB7, PCG-PC7
WRITE, RES, RS2-RSO, CS
Output Capacitance
(Vin = OV, TA = 25°C, f = 1.0 MHz)
IOH
IOL
ICC
Cin
Cout
-200
3.2
-
-
-1000
-
50
7
-7
Note: Negative sign indicates outward current flow, positive indicates inward flow.
MAX
VCC
+0.8
± 2.5
±10
VCC
0.4
-
-
100
10
10
UNIT
V
V
fUA
IJA
V
V
IJA
mA
mA
pF
pF
2-78


3Pages


6525 電子部品, 半導体
6525 INTERNAL REGISTERS
MPS
6525
ADDRESS
REGISTER BITS
REGISTER NAME
COMMENT
RS2 RSl RSO MC
000X
0 0 1X
0 100
0 101
0 11X
100X
10 10
1011
1 10 X
1111
07 De 05 D4 03 02 01 DO
PAl PA6 PA5 PA4 PA3 PA2 PAl PAO
PB? PB6 PB5 PB4 PB3 PB2 PBl PBO
PC? PC6 PC5 PC4 PC3 PC2 PCl PCO
CB CA IRQ IL4 IL3 IL2 ILl ILO
DA? DA6 DA5 DA4 DA3 DA2 DAl DAO
DB? DB6 DB5 DB4 DB3 DB2 DBl DBO
DC? DC6 DC5 DC4 DC3 DC2 DCl DCO
- - - M4 M3 M2 Ml
CBl CBO CAl CAO IE4 IE3 IP
- - - AI4 AI3 AI2 All
MO
MC
AIO
Port Register A (PRA)
Port Register B (PRB)
Port Register C (PRC)
Port Register C (PRC)
Data Direction
Register A (DDRA)
Data Direction
Register B (DDRB)
Data Direction
Register C (DDRC)
Interrupt Mask Register
Control Register (CR)
Active Interrupt Register(AI R}
Handshake and Interrupt Latches (MODE 1)
O=lnput; 1=Output
O=lnput; 1=Output
O=lnput 1=Output (MODE 0)
O=Mask; 1=Enable (MODE 1)
Mode Selected by MC
6525 FUNCTIONAL DESCRIPTION
Control Register (CR)
The bits of the control register select the various operating
modes of the 6525. Although the exact function of each bit is
explained throughout tne functional description. the func-
tions are summarized here for convenience.
I!cONTROL f~EGISTER BIT
76 5 4
0I
IIFUNCTIONAL DESIGNMIONICBl CBo CAl CAO IE4 IE:! IP MC
-~' ~CB L,", Coo,",
J .CA Line Control
I
14 Active Edge Select
13 Active Edge Select - - - - -_ _ _ _ _ _-'
Interrupt Priority _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Enable
Mode Control
MODE 0 - (MC=O)
In Mode 0, three 8 bit bi-directional ports (A, B, C) are
available on the 6525. Each port has two associated readl
write registers:
Data Direction Registers (DORA, DDRB, DDRC)
Each bit of the data direction registers controls the
EDD;b;'corresponding pin of the associated port as follows:
Direction of port pin
Input (Output driver disabled)
Output (Output driver enabled)
Port Registers (PRA, PRB, PRC)
Reading the Port Register returns the logic states of the
associated port pins. The pin voltage levels must meet the
VIH and VIL specification limits to ensure valid data. (Exces-
sive loading of the output driver may cause the data read to
differ from the expected output.) If the port pin is pro-
grammed as an output by the DDR. the output driver is set to
the last data written to the corresponding PR bit.
MODE 1 - (MC=1)
In Mode 1, the 6525 provides 2 8-bit bi-directional ports (A
and B) as in Mode O. By writing MC=1 , Port C is automati-
cally converted to a 5 level priority interrupt controller with
interrupt output (I RQ) and a handshake control line for each
port (CA and CB).
MODE 0 PIN NAMES PC? PC6 PC5 PC4 PC3 PC2 PCl PCO
MODE 1 PIN NAMES CB CA IRQ 14 13 12 11 10
Port Register C - PRC (Mode 1)
All bits of the PRC can be read as in Mode 0 but the state
of the interrupt latches, rather than the interrupt pins, is
returned in the five low order bits of PRC. Writing "0" to a PRC
bit clears the corres.Q0nding interrupt latch but has no effect
on the CA, CB, or IRO outputs. Writing" 1" to a PRC bit has no
effect on Mode 1.
MODE 0 BIT NAMES
MODE 1 BIT NAMES
2-81

6 Page



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