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6509 の電気的特性と機能

6509のメーカーはCommodoreです、この部品の機能は「MICROPROCESSOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 6509
部品説明 MICROPROCESSOR
メーカ Commodore
ロゴ Commodore ロゴ 




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6509 Datasheet, 6509 PDF,ピン配置, 機能
C o m m o d o r e Semiconductor G roup
o division of Commodore Business Machines, Inc.
950 Rirrenhouse Rood. Norristown PA 19400 • 215/666-7950 • TWX 510-660-4168
IM M O S
6509 MICROPROCESSOR WITH MEMORY MANAGEMENT
DESCRIPTION
The 6509 is a low -cost m icroprocessor capable of solving a broad range of sm all-system s and
memory managem ent problems at m inimum cost to the user.
A m em ory m anagem ent system allows for up to One M ega-Byte of m em ory for ease in down loading
languages, operating systems or other data.
The Three-State sixteen-bit Address Bus allows Direct Memory Accessing (DMA) and m ulti­
processor systems sharing a com m on memory while the Four-bit Extended Address Register allows for
up to one Mega-byte of data storage.
The internal processor architecture is identical to the Com m odore Sem iconductor Group 6502 to
provide software compatibility.
FEATURES OF THE 6509
■ Memory management
■ On board clock logic
■ Addressable m em ory range of up to 1 M bytes
■ Single +5 volt supply
■ N channel, silicon gate, depletion load technology
■ Eight bit parallel processing
■ 56 Instructions
■ Decimal and binary arithmetic
■ Thirteen addressing modes
■ True indexing capability
■ Programmable stack pointer
■ Variable length stack
■ Interrupt capability
■ 8 Bit Bi-Directional Data Bus
■ Program Addressable memory range of up to 65K bytes
■ Direct memory access capability
■ Bus compatible with M6800
■ Pipeline architecture
■ 1 MHz, 2 MHz, and 3 MHz operation
■ Use with any type or speed memory
PIN CONFIGURATION
R EA D Y C=
IRQ- cz
SYNC cz
1
2
3
NMt cz 4
AEC
VDD
A0
A1
A2
A3
A4
A5
A6
cz
cz
cz
c=
cz
c=
c:
cz
cz
5
6
7
8
9
10
11
12
13
A7 cz 14
A8 cz 15
A9 cz 16
A10 cz 17
A 1 1 cz 18
A12 cz 19
A13 cz 20
6509
40 3 0 2 IN
39 z : RESET
38 Z3 0 1 IN
37 => R /W
36 =3 DO
35 ZJ D1
34 ZD D2
33 Z1 D3
32 3 D4
31 D5
30 D6
29 D7
28 SO
27 PO
26 P1
25 P2
24 P3
23 A15
22 A14
21 VSS
10/86

1 Page





6509 pdf, ピン配列
6509 CHARACTERISTICS
MAXIMUM RATINGS
RATING
SUPPLY VOLTAGE
INPUT VOLTAGE
OPERATING TEMPERATURE
STORAGE TEMPERATURE
SYMBOL
Vm
tA
t STG
VALUE
—0.3 to + 7.0
- 0 .3 to + 7.0
0 to + 70
- 5 5 to + 150
UNIT
Vdc
Vdc
C
C
This d e v ic e c o n ta in s in p u t p ro te c tio n a g a in s t
d a m a g e d u e to h ig h sta tic vo lta g e s or
e le c tric fields; how ever, p re c a u tio n s s h o u ld
be taken to avoid a p p lica tio n of voltag es
h ig h e r than the m axim um rating.
ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, Vss = 0, Ta = 0 to + 70 C)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
Input High Voltage
0 - • ®2(in)
Input High Voltage
RES, P0-P r IRQ, Data
Input Low Voltage
®2 (in)
RES, Pa-P ? IRQ, Data
VIH V c c -0 .2
Vcc + 1 ,0V
2.0
-
VIL 0.2
— — 0.8
Input Leakage Current
(Vjn = 0 to 5.25V, Vcc = 5.25V)
Logic
0 j(in )
Iin
2.5
— — 100
Three State (Off State) In p u t Current
(Vin = 0.4 to 2.4V. V cc = 5.25V)
Data Lines
ITSI
10
O utput H igh Voltage
(lO H = 00/uAdc, Vcc = 4,75V)
Data. A0-A1 5, R/W, P0-P-
VOH
2.4
Out Low Voltage
(lO L = 1 Sm Adc. Vcc = 4.75V)
Data. A0-A15. R/W, P0-P :
VOL
+0.60
Power Supply Current
C a p a c ita n c e
Vjn = 0, Ta = 25 C. f = 1 MHz)
Logic, P0-P7
Data
A0-A1 5, R/W
0,
(Z>2
ICC
C
Cm
Cout
C<2>,
C02
— 125
30
— 50
10
15
12
50
80
U N IT
Vdc
Vdc
Vdc
Vdc
/UA
pA
a *a
Vdc
Vdc
mA
PF
3


3Pages


6509 電子部品, 半導体
(C CHARACTEF ISTICS
1 MHz TIM IN G
2 MHz TIM IN G
ELECTRICAL CHARACTERISTICS (VCC = 5V + 5%, VSS = OV, T^ - 0° -70° C)
Clock Timing
CH ARACTERISTIC
SYMBOL
C ycle Time
C lo ck P uise W idth 01
(M easured at VCC - 0 2V) 02
tcyc
PW H 0,
PWH02
Fall Time, Rise Tim e
(M easured from 0.2V to VCC - 0.2V)
Delay Tim e between C locks
(M easured at 0.2V)
tf . tr
Read/Write Timing (Load = 1 TTL)
MIN.
1000
430
470
__
0
MAX.
_
_
25
_
M IN
500
215
235
_
0
MAX.
-
15
_
C H A R A C T E R IS T IC
Read, W rite Setup Tim e from 6509
A ddress Setup Tim e from 6509
M emory Read Access Time
Data Stability Tim e Period
Data Hold Tim e-R ead
Data Hold Tim e-W rne
Data Setup Time from 6509
A ddress Hold Tim e
R /W Hold Time
Port O utput Data Valid
(M em ory Managements
RDY Setup Time
S.O Setup Tim e
SYNC Setup Time from 6509
Address Enable Setup Time
Data Enable Setup Tim e
Address Disable ’ See Note 1
Data Disable *See Note 1
’ Note 1 — 1TTL Load
CL = 30pf
SY M 80L
T RWS
t ADS
tacc
t DSU
t HR
t HW
t MDS
t ha
t hrw
t pdw
t rdy
tS 0
t syn c
t aes
t des
t aed
t ded
M IN
-
-
-
100
10
10
-
10
10
'
100
-
-
-
-
-
MAX.
300
300
575
-
-
-
200
-
-
300
-
-
350
75
120
120
130
MIN MAX
- 150
150
- 300
50 -
10 -
10 -
- 100
10 -
10 -
_ 150
50 _
50 _
- 175
- 75
- 120
- 120
- 130
3 MHz TIM IN G
M IN
333
145
165
_
0
MAX
15
__
M IN
-
-
50
10
10
-
10
10
MAX.
125
125
250
-
-
-
100
-
-
_ 125
15 -
50 -
120
- 75
- 120
- 120
- 130
U N IT S
ns
ns
ns
ns
ns
U N IT S
ns
ns
ns
ns
ns
ns
ns
ns
ns
jus
ns
ns
ns
ns
ns
ns
ns
SIGNAL DESCRIPTION
Clocks (0-1,02)
The 6509 requires a two phase non-overlapping clock
that runs at the Vcc voltage level.
Address Bus (A g-A -^)
The tri-state outputs are TTL com patible, capable of
driving one standard TTL load and 130 pf.
Data Bus (DQ-D7)
Eight pins are used for the data bus. This is a Bi-
Directional bus. transferring data to and from the device
and peripherals. The outputs are tri-state buffers capable
of driving one standard TTL load and 130 pf.
Reset
This input is used to reset or start the m icroprocessor
from a power down condition. During the tim e that this line
is held low, writing to or from the m icroprocessor is
inhibited. When a positive edge is detected on the input,
the m icroprocessor will im m ediately begin the reset
sequence.
After a system initialization tim e of six c lo ck cycles, the
mask interrupt flag will be set and the m icroprocessor will
load the program counter from the memory vector
locations FFFC and FFFD. This is the start location for
program control.
After V cc reaches 4.75 volts in a power up routine, reset
must be held low for at least two clock cycles. At this tim e
the R /W signal will becom e valid.
When the reset signal goes high following these two
clock cycles, the m icroprocessor will proceed with the
normal reset procedure detailed above.
6

6 Page



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